PCINLIFE：英特尔Tera级别处理器架构图全球抢先曝光

Edison

w00t)

Edison

连cache设计都是异质方式。

CELL的确是引领了新的处理器更新潮流，不过碍于生产工艺问题，没能把PPU、SPE DP做满，不过这些问题可能会随着CELL DP的问世而变得不再是什么问题了。

其实PPU就一个2-issue port，又有FGMT，的确没啥必要上OoO那么复杂而不讨好的设计。

Illuminati

without OoO ?? this is gonna be a disaster in the x86 world

Edison

http://www.pcinlife.com/news/har ... 1159234722d222.html

AFXIF

到底是什么？
一片里面集成高中低三档次的核心么？
然后核心都是X86的。

spinup

指出点小问题：
scalable On-die Interconnect Fabric
这个fabric是结构/构造的意思

Edison

我已经更改为互连结构了。

pjtomtai

原帖由 Edison 于 2006-9-26 10:01 发表
我已经更改为互连结构了。

这"scalable on-die interconnect fabric"极有可能就是刚出样的on-die laser interconnect (物理实现方式),基于CSI (逻辑).
http://www.dailytech.com/article.aspx?newsid=4200

Edison

AT THE ONE of numerous press briefings happening at IDF, several key figures at Intel were discussing the future of Intel and how will things develop with the changing face of computing as such. Even though the products aren't even close to coming out the door, the company's marketing department has everything ready - and you will get bombarded with bombastic Tera-Scale Computing marchitecture campaigns.

The Tera-Scale is a nice marchitecture name for orientation on mini-cores and mini-threads, which are set to send current dual and quad-core counterparts into the oblivion.

Abel Weinrib stated that parallelism is "inevitable", and the company is now talking about removing obstacles in order to achieve maximum usability and bandwidth. We'll talk more about Tera-Scale marchitecture in follow-up articles, and just leave you with a picture of the very first mini-core effort from Intel's development team from Far East.



The experimental IA-32 mini-core is currently being run in a form of Field Programmable Grid Array, also known as FPGA. And yes, your eyes aren't fooling you: the ASUS motherboard which Intel's Asian engineers are using is indeed old 430HX Triton chipset based one, equipped with 72-pin EDO SIMMs. The FPGA is using Socket 7 for housing four different PCBs, and everything looks as earliest stages of development.



But, the FPGA is still able to run Windows XP- even though it's working at a measly 1.91MHz (not a typo) at 97% processor load. µ

Edison

FPGA模拟IA32，跑2MHz不够，主板不需要怎样讲究。

keepwalking

CELL为CPU注入全新活力OR概念

Prescott

http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2840&p=6

Intel's Answer to Cell: The Teraflop chip

When Sony's Cell architecture was first introduced, everyone looked to Intel for an answer - and the best we got was that the foreseeable future of multi-core computing would be x86 based. When Cell was first announced, Pro Acessor with 9 cores was unheard of as we were just being introduced to Intel's dual core offerings and quad core was just a pipedream. By the time the PlayStation 3 launches, dual socket Xeon systems will be able to have the power of 8 very powerful x86 cores and all of the sudden the number of cores in Cell stops being so impressive. But there is quite a bit of merit to Cell's architecture and design, as Intel has alluded to many times in the past, and today Intel showcased Pro Acessor that is very similar in design.



Intel outfitted a single chip with a total of 80 very simply cores, that combined can execute a peak rate of 1 trillion floating point operations per second. Each core uses a very simple instruction set, only capable of executing floating point code, and are individually quite weak. But the combined power of the 80 cores is quite impressive, and it's directly taking a page from the book of Cell. While Cell's SPEs are likely more powerful than each of the cores in the teraflop chip, the design mentality is similar.



The facial expression is a side effect of holding a wafer of teraflop chips

Intel showed off a wafer of these teraflop chips, with a target clock speed of 3.1GHz and power consumption of about 1W per 10 gigaflops - or 100W for 1 TFLOP. The chip is simply a technology demo and won't be productized in any way, but in the next 5 years don't be too surprised if you end up seeing some hybrid CPUs with a combination of powerful general purpose cores with smaller more specialized cores.

ximimi

没有优秀的内部总线的话，几个简单u并在一起

来个复杂组合图形处理，就都死了

效率锐减到原来1/10-1/100w00t)

流水线重过，不能一周期完成，互相抢占，wait都hang死了

做显卡配一个定制的fpga还差不多

和rsx地位差不多

[ 本帖最后由 ximimi 于 2006-9-27 11:51 编辑 ]

Edison

"The 80-core processor consists of eight simple floating-point cores that each implement a small, stripped-down, non-x86 ISA. These cores are arranged in a tile pattern and connected to each other by means of an on-chip network. Note that these cores are almost certainly in-order, and are certainly less complex than the Cell processor's SPEs. The whole thing is very reminiscent of Sun's Niagara, and in fact I've heard that internally Intel uses their own little water-based metaphor for it; they call it the "sea of cores" approach. "

"You're probably wondering what the point of an 80-core processor is, when PS3 programmers are moaning about having to code for a chip with a mere seven small, in-order floating-point cores. This question has few answers, depending on how you approach it.

In the near-term, the point of this terascale chip is that it's a research project. The individual cores are very simplified, and they don't implement a standard ISA, because right now they're there for research purposes. (I'd expect the cores to get more complex, and maybe to offer more than just floating-point, in Pro Aduction model.) So the chip as a whole provides a platform for tooling around with massively multicore architectures, and figuring how to organize them, connect them to memory, program them, and generally bring ideas from the drawing board into the lab. In other words, this chip is Pro Atotype, and it points in a direction that Intel thinks they'll eventually take.

From a manufacturing and hardware design standpoint, the main problems that go with making use of an 80-core processor are interconnect- and memory latency-related. So Intel is clearly trying to solve those with TSVs and the laser interconnect technology, so that they can make usable systems built around such massively multicore chips.

This brings me to the long-term part of the question about the point of an 80-core processor. Software developers will point out that the only computing problems that could use the muscle of an 80-core chip like this exist in the rarified realm of high-performance computing, where programmers simulate weather patterns and nuclear blasts and whatnot. In the consumer software market, software architects are struggling to make use of the embarrassment of computational riches provided by dual-core processors, quad-core processors, and (most recently) GPUs.

All of this is true, as far as it goes, but I can't help but think that if such systems are widely available in the next decade, entrepreneurs will come up with a ways to make money from them. The nagging issue here is that I have no idea what a mass-market 80-core software application looks like, and neither does Intel (or Microsoft, or Sun, or IBM, etc.).

So to sum up, in the short-term, the terascale chip is a research platform for working out the kinks of massively multicore system and software design. In the long-term, this endeavor definitely has an air of "if we build it, will they come?" about it. But too many hardware makers are moving in this direction for the rest of the industry not to follow them. So even though Intel is forging ahead into uncharted territory with this "sea of cores" initiative, they're not doing so alone. ”

ximimi

Note that these cores are almost certainly in-order, and are certainly less complex than the Cell processor's SPEs

:p :p