HyperTransport interconnect technology is a high-performance, high-speed, high-bandwidth, point-to-point link that provides the lowest possible latency for chip-to-chip links. HyperTransport technology provides a flexible, scalable interconnect architecture designed to reduce the number of buses within the system, provide a high-performance link for applications ranging from embedded systems, to personal computers and servers, to network equipment and supercomputers.
HyperTransport technology's aggregrate bandwidth of 22.4GB/sec represents better than a 70-fold increase in data throughput over legacy PCI buses. While providing far greater bandwidth, HyperTransport technology complements legacy I/O standards like PCI as well as emerging technologies like PCI-X and PCI Express.
The HyperTranport Specification is clearly defined and maintained by the HyperTransport Consortium. The non-profit consortium publishes the specification, drives the development of future HyperTransport specifications and manages all specification issues. This enables the developer to confidently implement HyperTransport technology with the assurance that the resulting system will be interoperable with other HyperTranport-based subsystems.