标题: 5.2GHz IBM 公布全球最快处理器 z196 细节 [打印本页] 作者: Edison 时间: 2010-8-25 12:11 标题: 5.2GHz IBM 公布全球最快处理器 z196 细节 IBM revealed more details of its 5.2-GHz chip on Tuesday, the fastest microprocessor ever announced. Don't bet that you'll ever be able to buy it, though.
At the Hot Chips 2010 conference in Palo Alto, IBM executives described the z196, which will power its Z-series of mainframes, which can cost hundreds of thousands of dollars, if not over a million. IBM will ship the chip in September, said Brian Curran, an IBM distinguished engineer. The mainframe itself was announced in July.
IBM also previously claimed the title of fastest microprocessor with the POWER6 chip, which ran at speeds of up to 4.6 to 4.7 GHz, and its own z10, a 2008 chip which ran at speeds of up to 4.4 GHz.
IBM defines the z196 as one of the few remaining CISC chips, which allows for bulky, large programs that can require much more memory to execute in than RISC chips, including the PowerPC and ARM embeddded processors, among others.
The z196 contains 1.4 billion transistors on a chip measuring 512 square millimeters fabricated on 45-nm PD SOI technology. It contains a 64KB L1 instruction cache, a 128KB L1 data cache, a 1.5MB private L2 cache per core, plus a pair of co-processors used for cryptographic operations.
In a four-node system, 19.5 MB of SRAM are used for L1 private cache, 144MB for L2 private cache, 576MB of eDRAM for L3 cache, and a whopping 768MB of eDRAM for a level-four cache. All this is used to ensure that the processor finds and executes its instructions before searching for them in main memory, a task which can force the system to essentially wait for the data to be found—dramatically slowing a system that is designed to be as fast as possible.
The chip uses 1,079 different instructions, Curran said. Of these, 75 can be used by millicode only, with 219 executable by millicode; an additional 24 instructions are conditionally executed by millicode. (Millicode is an internal term used at IBM for instructions internally executed by the processor, slightly bulkier than the "microcode" used by other chips.) The chip can use 211 medium instructions cracked into two or more instructions at issue, with 269 dual issued. The remaining 340 instructions are RISC-like, Curran said.作者: CC9K 时间: 2010-8-25 12:14
In a four-node system, 19.5 MB of SRAM are used for L1 private cache, 144MB for L2 private cache, 576MB of eDRAM for L3 cache, and a whopping 768MB of eDRAM for a level-four cache.