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标题: 32nm HP的工艺性能比较 [打印本页]

作者: PRAM 时间: 2010-9-17 16:00
标题: 32nm HP的工艺性能比较
本帖最后由 PRAM 于 2010-9-17 16:02 编辑

at 1.0V and 100nA/um Ioff.	CGP（CGP越小，晶体管密度越大）	EOT/TOX(越薄越好)	NMOS	PMOS
INTEL 32NM HP	112．5	0.9	1620	1370
IBM 32NM SOI	130	1.2	1550	1220
TSMC 28NM HP	117	0.9	1360	960

作者: xf-108 时间: 2010-9-17 16:38
同样的2M SRAM，intel 32nm面积是最大的啊。

作者: PRAM 时间: 2010-9-18 08:55

同样的2M SRAM，intel 32nm面积是最大的啊。
xf-108 发表于 2010-9-17 16:38

SRAM DIE SIZE更大是出于降燥的考虑

作者: PRAM 时间: 2010-9-18 09:00
POWRPC 9:46:14
INTEL 32NM的contached gate pitch小于TSMC和IBM的28NM是不是因为INTEL的design rule比较特别？
Roy.Yu 17:36:14
性能要求不一样，所有design rule要求也不一样
Roy.Yu 17:36:45
一般而言，intel的工艺比foundry的下一代还要tight
Roy.Yu 17:37:04
所以他的32小于别人的28很正常的

作者: PRAM 时间: 2010-9-18 09:07
POWRPC  10:20:28
At IEDM, Intel manager Paul Packen said Intel's flagship 32 nm technology achieved record drive current levels, with the PMOS transistor showing a 35% drive current improvement over the 45 nm PMOS device. "For the first time, linear drive currents on the PMOS have overtaken NMOS," he said. The sharp gain in PMOS performance comes partly by adding germanium to the SiGe stressors, and from the replacement-gate process.
Intel Corp. presented details on its 32 nm logic technology at the International Electron Devices Meeting (IEDM), reporting that its fourth-generation strain techniques have boosted the PMOS performance to a historic point. "For the first time, linear drive currents on the PMOS have overtaken NMOS," said Paul Packan, 32 and 15 nm technology programs manager.

For the oft-quoted saturated drive current, the 32 nm NMOS value remains higher, at 1.62 mA/μm Idsat compared with 1.37 mA/μm for the 32 nm PMOS transistor. Packan said the PMOS linear drive current (ldlin) reached 0.24 mA/μm, a 35% improvement over the 45 nm PMOS transistor. The NMOS device Idlin gained a 20% improvement, partly from a raised source-drain architecture, reaching a linear drive current of 0.231 mA/μm. Linear drive current is important because transistors rarely get to full saturation, making Idlin a meaningful metric for real-world device operation.

With NMOS and PMOS now in rough parity, designers can adjust the size of the PMOS transistors to their needs, said Mark Bohr, a senior fellow at Intel. "For many generations, there was a 2:1 ratio between the NMOS and PMOS," largely caused by inherently different mobilities between electrons and holes. "At the 32 nm generation, our saturation and linear drive currents are closer to being matched; we are getting very close." That means for the Westmere processor Intel designers could create circuits with smaller PMOS transistors in some cases, Bohr said.
The sharp gain in PMOS performance comes partly by adding more germanium to the SiGe stressors, to a 40% level. Also, "we are moving the SiGe closer to the channel at the 32 nm generation, which is challenging at these dimensions," Bohr said.

The replacement gate technique adds another boost, rivaling that of the SiGe stressors. Before high-k/metal gate technology was introduced, the polysilicon electrode was neutral in terms of strain on the PMOS channel. With the replacement gate, or gate-last, technology, removal of the sacrificial gate allows the SiGe stress regions to exert a stronger tensile strain on the channel, reaching 2 GPaFor the NMOS, the raised source and drain reduces resistance, "helping to mitigate the pitch scaling issues," Packan said. By moving transistors closer together, there is less room for stress regions. Though in previous interviews Bohr has not been positive about the value of SiC stressors on the NMOS channel, he declined to comment on whether Intel is using SiC at the 32 nm node.

Although Intel remains on a Moore's Law pace in terms of contact gate pitch scaling, with a 112.5 nm pitch, shrinking is no longer delivering the speed improvements seen in past generations, Packan said. With smaller dimensions, less material can be deposited to add strain. And threshold voltages have crept up slightly in recent years at the same Ioff levels.

"Traditional scaling is losing steam," Packan told the standing-room-only Wednesday IEDM session on leading-edge CMOS. He estimated that were it not for the additional benefits of higher strain, performance actually would have declined for the 32 nm transistors. One reason, Bohr said, is that to counter short channel effects in the aggressively scaled gates the channel must receive higher dopant levels, causing threshold voltages to rise and slowing down the transistor.

"We need a new paradigm for performance improvement," Packan said.

Though several participants at IEDM said CMOS scaling is likely to slow to a three-year pace, Bohr said Intel plans to stay on a two-year cadence. The Westmere processors are shipping now from two Intel fabs to computer vendors, and the 22 nm technology is on pace to ship two years later. Not only does Intel want to remain ahead of its MPU competition, its computer customers need faster MPUs every two years so they can sell new systems to their customers, he said.
  Roy.Yu 10:24:10
美国人做研发确实很牛的，都是实干的，小日本也是的
Roy.Yu 10:24:36
新工艺居然可以改变design layout了
Roy.Yu 10:24:53
pmos不用再画那么大了，呵呵，牛哦

作者: spinup 时间: 2010-9-18 09:07

PRAM 发表于 2010-9-17 16:00

ibm的NMOS/PMOS数字还赚便宜呢

作者: PRAM 时间: 2010-9-18 09:09
POWRPC 10:01:48
可不可以这样说：高性能工艺  INTEL略微领先IBM  通用工艺IBM和TSMC差不多

Roy.Yu 10:02:30
不是略微，而是大幅度的；  Roy.Yu 10:02:50
其他的都没有可比的高性能工艺，我是说同一个node
Roy.Yu 10:03:13
别人的跟他比落后一般1到2代的样子
POWRPC 10:04:43
你怎么看INTEL坚持完全独立开发先进工艺而不和其他厂家合作

POWRPC 10:05:21
因为TSMC实际上和NXP，TI一直都在合作

Roy.Yu 10:05:32
因为他的产品跟别人的不一样，没有合作的空间
Roy.Yu 10:05:39
另外还有技术外泄的问题  Roy.Yu 10:05:58
其他家的产品或者工艺都有相容性，所以可以合作
POWRPC 10:06:32
据说INTEL相当多的EDA工具都是自己开发的

Roy.Yu 10:07:28
那是由于太有钱了，没有感觉到业界的压力

作者: PRAM 时间: 2010-9-18 09:12

ibm的NMOS/PMOS数字还赚便宜呢
spinup 发表于 2010-9-18 09:07

赚便宜?赚什么便宜?

作者: spinup 时间: 2010-9-18 09:14

赚便宜?赚什么便宜?
PRAM 发表于 2010-9-18 09:12

别那么敏感嘛。我说的话确实有点歧义。ibm的数据要放在这个表里的话还要打折扣---对intel和tsmc有点不公平

作者: PRAM 时间: 2010-9-18 09:17
本帖最后由 PRAM 于 2010-9-18 09:18 编辑

POWRPC
15:23:33
UMC为什么不加入IBM联盟，看它根本撑不了多久了，TSMC 40NM出了问题，UMC连65NM都搞不定

日期:2009-8-9
POWRPC
14:03:08
IBM联盟metal gate只在32nm以下用，并且至今也不成熟---请问是不是这样的

Roy.Yu 14:09:42
没错，你的消息很强哦
POWRPC
14:10:19
IBM同一个节点为什么开发几套工艺

POWRPC
14:11:12
你看45NM，HIGH-K那两款明显是不会量产的

POWRPC
14:11:37
就光是研究用吗？

Roy.Yu 14:13:06
IBM45的没有high k & metal gate
POWRPC
14:13:25
我发个你那张图片上有

Roy.Yu 14:15:23
估计是SOI的吧
POWRPC
14:15:41
SOI high k都有

Roy.Yu 14:17:04
一般一个node有2到3套工艺，基于性能要求的不一样  POWRPC
14:17:26
但是HIGH-K那两款明显是不会量产的啊

Roy.Yu 14:18:14
IBM是做IP的，不管能不能量产                                                                                                                                  POWRPC
14:19:10
我想IBM之所以搞不过INTEL，就是商业性不如INTEL

Roy.Yu 14:19:35
IBM没有产品！！！！

POWRPC
14:20:02
有，POWER,POWER PC

Roy.Yu 14:22:57
TSMC的工艺就是性价比高，IBM只是研究用的，转换成实际量产需要做的很多

作者: PRAM 时间: 2010-9-18 09:23

别那么敏感嘛。我说的话确实有点歧义。ibm的数据要放在这个表里的话还要打折扣---对intel和 ...
spinup 发表于 2010-9-18 09:14

打折扣?

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper .
5200664 abstract .

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  .
Greene, B.  Liang, Q.  Amarnath, K.  Wang, Y.  Schaeffer, J.  Cai, M.  Liang, Y.  Saroop, S.  Cheng, J.  Rotondaro, A.  Han, S.-J.  Mo, R.  McStay, K.  Ku, S.  Pal, R.  Kumar, M.  Dirahoui, B.  Yang, B.  Tamweber, F.  Lee, W.-H.  Steigerwalt, M.  Weijtmans, H.  Holt, J.  Black, L.  Samavedam, S.  Turner, M.  Ramani, K.  Lee, D.  Belyansky, M.  Chowdhury, M.  Aime, D.  Min, B.  van Meer, H.  Yin, H.  Chan, K.  Angyal, M.  Zaleski, M.  Ogunsola, O.  Child, C.  Zhuang, L.  Yan, H.  Permanaa, D.  Sleight, J.  Guo, D.  Mittl, S.  Ioannou, D.  Wu, E.  Chudzik, M.  Park, D.-G.  Brown, D.  Luning, S.  Mocuta, D.  Maciejewski, E.  Henson, K.  Leobandung, E.
IBM Syst. & Technol. Group, IBM Semicond. R&D Center (SRDC), Hopewell Junction, NY, USA

This paper appears in: VLSI Technology, 2009 Symposium on
Issue Date: 16-18 June 2009
On page(s): 140 - 141
Location: Honolulu, HI
Print ISBN: 978-1-4244-3308-7
INSPEC Accession Number: 10826268
Date of Current Version: 11 八月 2009

Abstract
This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 mum2. Vmin operation down to 0.6 V in a 16 Mb SRAM array test vehicle has been demonstrated. Aggressive ground rules are achieved with 193 nm immersion lithography. High performance is enabled by high-k/metal gate plus innovation on strained silicon elements including embedded SiGe and dual stress liner (DSL). Gate lengths down to 25 nm have been demonstrated enabling performance without the power penalty from gate capacitance. AC drive currents of 1.55 mA/um and 1.22 mA/um have been achieved at an off-state of 100 nA/mum and VDD of 1 V for NFET and PFET, respectively. For the first time, we have also demonstrated that SOI maintains performance benefit over bulk silicon in high-k/metal gate and 32 nm ground rules.

作者: PRAM 时间: 2010-9-18 09:26
Packan, P.; Akbar, S.; Armstrong, M.; Bergstrom, D.; Brazier, M.; Deshpande, H.; Dev, K.; Ding, G.; Ghani, T.; Golonzka, O.; Han, W.; He, J.; Heussner, R.; James, R.; Jopling, J.; Kenyon, C.; Lee, S.-H.; Liu, M.; Lodha, S.; Mattis, B.; Murthy, A.; Neiberg, L.; Neirynck, J.; Pae, S.; Parker, C.; Pipes, L.; Sebastian, J.; Seiple, J.; Sell, B.; Sharma, A.; Sivakumar, S.; Song, B.; St. Amour, A.; Tone, K.; Troeger, T.; Weber, C.; Zhang, K.; Luo, Y.; Natarajan, S.;
Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA

This paper appears in: Electron Devices Meeting (IEDM), 2009 IEEE International
Issue Date: 7-9 Dec. 2009
On page(s): 1 - 4
Location: Baltimore, MD
E-ISBN: 978-1-4244-5640-6
Print ISBN: 978-1-4244-5639-0
INSPEC Accession Number: 11207473
Digital Object Identifier: 10.1109/IEDM.2009.5424253
Date of Current Version: 29 三月 2010

Abstract
A 32 nm logic technology for high performance microprocessors is described. 2nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32 nm or 28 nm logic technology. NMOS drive currents are 1.62 mA/um Idsat and 0.231 mA/um Idlin at 1.0 V and 100 nA/um Ioff. PMOS drive currents are 1.37 mA/um Idsat and 0.240 mA/um Idlin at 1.0 V and 100 nA/um Ioff. The impact of SRAM cell and array size on Vccmin is reported.

作者: 史前泡菜 时间: 2010-9-18 16:27
进来学习，虽然看不懂。

作者: 直流电 时间: 2010-9-18 16:28
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作者: aaa777ly 时间: 2010-9-18 16:51
**一群群…

作者: potomac 时间: 2010-9-18 17:52
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作者: skywalker_hao 时间: 2010-9-18 18:05

IBM也有2个工厂。
不过一个是快淘汰的厂。

工艺和工厂数目成正比。
谁的厂多，说明谁的工艺领先。
[l ...
potomac 发表于 2010-9-18 17:52

用着TSMC 40nm的nv泪流满面

作者: lfs5153 时间: 2010-9-18 20:15
面积大散热好，各有千秋

作者: xf-108 时间: 2010-9-18 20:23
本帖最后由 xf-108 于 2010-9-18 20:26 编辑

IBM也有2个工厂。
不过一个是快淘汰的厂。

工艺和工厂数目成正比。
谁的厂多，说明谁的工艺领先。
[l ...
potomac 发表于 2010-9-18 17:52

厂的数量跟工艺先进与否没有必然联系。

intel晶圆厂总数可能不是最多的，不过300mm晶圆厂绝对是最多的，现在总数至少是八座。不知道intel现在还保留了几座200mm晶圆厂。

作者: Prescott 时间: 2010-9-18 22:02
Intel工艺独步天下，这点无需置疑了。

作者: PRAM 时间: 2010-9-19 09:04

厂的数量跟工艺先进与否没有必然联系。

intel晶圆厂总数可能不是最多的，不过300mm晶圆厂绝对是最多的 ...
xf-108 发表于 2010-9-18 20:23

intel现在还保留了2座200mm晶圆厂,分别是FAB17和IFO

作者: PRAM 时间: 2010-9-19 09:23

厂的数量跟工艺先进与否没有必然联系。

intel晶圆厂总数可能不是最多的，不过300mm晶圆厂绝对是最多的 ...
xf-108 发表于 2010-9-18 20:23

这个你要看什么样的FAB,整个半导体业界，300MM FAB最多的是SAMSUNG,

作者: Cc. 时间: 2010-9-19 20:20
英特尔的工艺确实独步天下，无疑问的，这方面即使是IBM都无法比肩

作者: xf-108 时间: 2010-9-20 01:10
本帖最后由 xf-108 于 2010-9-20 10:03 编辑

http://tieba.baidu.com/f?ct=3356 ... word=amd#7953650825

Afan定律：AMD可以随意屏蔽核心廉价卖，说明了AMD 45nm生产成本非常低。
clarkdale/Gulftown那么小核心居然卖那么高天价，说明了intel 32nm生产成本非常高，良率非常低。

Afan原理：1、AMD史上价格定位最杯具，性能最窝囊的65nm系列是AMD史上猫利率最高的CPU。
2、AMD 45nm电气性能比intel 32nm还强。

作者: frankincense 时间: 2010-9-20 06:42

Afan定律：AMD可以随意屏蔽核心廉价卖，说明了AMD 45nm生产成本非常低。
clarkdale/Gulftow ...
xf-108 发表于 2010-9-20 01:10

AFAN公论:咱AMD上面有人(IBM)只要它动动指头,Intel就要玩完

作者: PRAM 时间: 2010-9-20 20:58

Afan定律：AMD可以随意屏蔽核心廉价卖，说明了AMD 45nm生产成本非常低。
clarkdale/Gulftow ...
xf-108 发表于 2010-9-20 01:10

所谓高性能的45NM,EOT相当于INTEL的90NM,电气性能是在at 1.0V and 200nA/um Ioff.得出的，而且PMOS性能不行。gate-first就是这儿搞不下去。所以这款45NM仅仅是研究用的

作者: PRAM 时间: 2010-9-20 20:59
For AMD, the goal was not only to shrink the physical dimensions but also to increase performance. Scaling transistors means better performance, but most of the dimensional scaling at 45 nm is related to gate and metal pitches rather than to length of the transistor gate or channel. The minimum gate length on Shanghai is 38 nm—a reduction of only seven percent from the 65-nm node. But the transistor performance is 19 percent better for the NFET and 23 percent better for the PFET compared with 65-nm generation transistors.

How'd they do that? The answer, in a word, is optimization. Although there are no new materials or techniques like adding an additional stressor for strained silicon engineering, AMD improved transistor performance by squeezing every last drop out of the performance-enhancing structures already in use at 65 nm. As usual, the starting point was a silicon-on-insulator (SOI) wafer as opposed to the bulk wafer technology used elsewhere. The rest of the transistor performance story relates to strain engineering.

On the NFET side, stress memorization stretches the n-channel, which is enhanced later in the process flow by the addition of a nitride tensile stress liner. The liner itself is scaled down at 45 nm to ensure the required strain is adequately supplied to the transistor channel to enhance electron mobility and subsequently increase the drive current. The gate-stack design is modified as well, with a new sidewall spacer design for 45nm.

The PFET performance improvement is more dramatic with drive current now up to 660 µA/µm compared with 510 µA/µm on 65-nm transistors. Again, this increased output current is the result of optimized compressive strain for the p-channel device. The new design of the PFET moves the embedded silicon-germanium source/drain regions closer to the channel to maximize the transfer of stress, thereby increasing hole mobility. Although shorter gate lengths are not driving the improvements, it is a reduction in dimensions that allows increased channel stress to provide the performance scaling. AMD 45-nm PFET design reduces the space from embedded

作者: PRAM 时间: 2010-9-20 21:02
We all want our Google results to come fast, so server-chip speed is important. Intel has a long history of pushing processor-speed performance ratings, and did so by designing transistors with high on currents to drive fan out gates quickly. In fact, Intel's 45-nm high-K metal gate transistors have the best peak drive currents on the market with 1.36µA/µm for NFETs and just over a milliamp for PFETs. Compared with Intel's speed-burners, a typical 45-nm transistor on AMD's Shanghai is a lot less powerful. I know very little about CPU benchmarks let alone server tests, but I know the speed performance for a Shanghai-based server would be limited at some point by the lower drive current available from the AMD 45-nm transistors.
The transistor drive current for AMD's 45-nm devices is much lower than that of the Intel HKMG transistors.

作者: 直流电 时间: 2010-9-20 21:15
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作者: spinup 时间: 2010-9-20 22:13

某些专业网站认为45nm的shanghai有23-24个FO4延迟。而intel的penryn则是18-20个FO4延迟。penryn最高大约3.3g。
根据这些数字如果amd的工艺只和intel相当，那shanghai连3g都应该爬不上........

作者: acqwer 时间: 2010-9-20 22:29
X5270 3.5G

只能到3G和只出到3G是2回事，装着看不到想不到是没用的。

作者: xeon-pan 时间: 2010-9-21 09:52

在这个交易和菜鸟的地方谈这个貌似假装...
直流电发表于 2010-9-20 21:15

这里曾经不是只有菜鸟的地方。你都05年注册的了，应该知道GZ。。。

作者: skywalker_hao 时间: 2010-9-21 10:03

一份半年前就应该人手一份的会议摘要被拿来当宝每天挤一点出来显眼

作者: skywalker_hao 时间: 2010-9-21 10:12
标题: 对比
本帖最后由 skywalker_hao 于 2010-9-21 10:14 编辑

X5270 3.5G

只能到3G和只出到3G是2回事，装着看不到想不到是没用的。
acqwer 发表于 2010-9-20 22:29

xeon总会有一款要高一点的嘛

不过5270和5272还不够震撼
3.4G的5492才震撼嘛
对比9775

作者: PRAM 时间: 2010-9-21 10:45

某些专业网站认为45nm的shanghai有23-24个FO4延迟。而intel的penryn则是18-20个FO4延迟。penryn最 ...
spinup 发表于 2010-9-20 22:13

你就YY下去吧

作者: PRAM 时间: 2010-9-21 10:45
本帖最后由 PRAM 于 2010-9-21 10:52 编辑

一份半年前就应该人手一份的会议摘要被拿来当宝每天挤一点出来显眼
skywalker_hao 发表于 2010-9-21 10:03

不知道是谁在显眼，

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IAR Systems supports new Freescale MCU families News and Outlook[发展动态] 2010-6-23 08:56
by RRAM  正常
Freescale debuts 64-bit Power core News and Outlook[发展动态] 2010-6-23 08:53
by RRAM  正常
Tilera, Quanta pack 512-core server in 2U chassis News and Outlook[发展动态] 2010-6-23 08:52
by RRAM  正常
Will Spansion succeed or fail again? News and Outlook[发展动态] 2010-6-23 08:51
by RRAM  正常
Freescale CEO: 'Connected intelligence' beating recession News and Outlook[发展动态] 2010-6-23 08:50
by RRAM  正常
Xilinx to offer three classes of FPGAs at 28-nm News and Outlook[发展动态] 2010-6-21 19:40
by RRAM  正常
Qualcomm delays dual-core Snapdragon for smart books News and Outlook[发展动态] 2010-6-19 10:09
by RRAM  正常
DAC: IC design bound for cloud computing News and Outlook[发展动态] 2010-6-18 09:53
by RRAM  正常
Apple's A4 dissected, discussed...and tantalizing News and Outlook[发展动态] 2010-6-18 09:49
by RRAM  正常
Qualcomm invests in optical module company News and Outlook[发展动态] 2010-6-17 10:35
by RRAM  正常
Intel tips 'resilient memories' for MPUs News and Outlook[发展动态] 2010-6-17 10:33
by RRAM  正常
Intel speeds up single-chip cloud computer News and Outlook[发展动态] 2010-6-17 10:32
by RRAM  正常
VLSI: Intel's 32-nm process ready for RF News and Outlook[发展动态] 2010-6-20 23:56
by obiwan  正常
Intel moves forward with floating-body R&D News and Outlook[发展动态] 2010-6-17 10:29
by RRAM  正常
Intel litho strategy change could propel ASML, says report News and Outlook[发展动态] 2010-6-16 20:18
by RRAM  正常
Qualcomm joins Sematech as first fabless member News and Outlook[发展动态] 2010-6-16 10:23
by RRAM  正常
Macronix paves the way for 3-D flash News and Outlook[发展动态] 2010-6-16 10:21
by RRAM  正常
TSMC, Tela trim logic die area by 15% News and Outlook[发展动态] 2010-6-17 13:43
by ncmoon  正常
Toshiba reports 16-nm nanowire transistor News and Outlook[发展动态] 2010-6-16 10:18
by RRAM  正常
Full Altera Stratix IV family in volume production News and Outlook[发展动态] 2010-6-15 17:26
by RRAM  正常
Nano-coating cools chips four times faster News and Outlook[发展动态] 2010-6-15 17:25
by RRAM  正常
IMEC ramps resistive RAM research News and Outlook[发展动态] 2010-6-15 17:24
by RRAM  正常
Samsung incites "foundry wars" with 32nm News and Outlook[发展动态] 2010-6-15 11:22
by RRAM  回收站
IBM's 'fab club' enters high-k era News and Outlook[发展动态] 2010-6-15 10:54
by RRAM  正常
PowerVR gets DirectX9, support News and Outlook[发展动态] 2010-6-12 12:15
by RRAM  正常
Analysis: Acquisitions reflect broadening view of EDA News and Outlook[发展动态] 2010-6-12 12:13
by RRAM  正常
IMEC set to take transistors 'sub-threshold' News and Outlook[发展动态]

作者: PRAM 时间: 2010-9-21 10:47

一份半年前就应该人手一份的会议摘要被拿来当宝每天挤一点出来显眼
skywalker_hao 发表于 2010-9-21 10:03

不知道是谁在显眼，丢人也要有个度，后面这个是反向分析得出的结论

作者: PRAM 时间: 2010-9-21 10:51
本帖最后由 PRAM 于 2010-9-21 10:56 编辑

ee.letters
入伍新兵

名誉值1  工作领域工作年资个人空间发短消息加为好友当前在线  1# 大中小
发表于 2009-3-19 16:43  只看该作者
求助: High-k gate-first 与High-k first, metal gate last比较?
目前只了解:
IBM alliance:  High-k gate-first, 工艺简单,与原有工艺类同,
Intel: High-k first, metal gate last, 性能好 x
不知道对不对.,
到底区别有哪些? 好处在哪?

IBM联盟有用metal gate呀. 为什么提的很少呢?

谢谢!

搜索更多相关主题的帖子: gate metal first last 求助

UID252313 帖子121 精华0 积分8 金币17  名誉值1  在线时间116 小时注册时间2006-7-27 最后登录2010-8-19 查看详细资料
引用报告评分回复 TOP
人生有多少价值，端视帮助多少人创造价值！

tellmewhy
论坛版主

名誉值50  工作领域PIE 工作年资4年个人空间发短消息加为好友当前离线  2# 大中小发表于 2009-3-20 09:50  只看该作者
IBM联盟metal gate只在32nm以下用，并且至今也不成熟，所以提得很少，前2个问题暂时不能回答你，因为涉及到某些机密以前有一个半导体工程师，非常认真负责，任何data都仔细check，老板压的AR都最快最完美的解决，无论多难的case，都能顺利的close，每天不做完事情坚决不肯走，终于有一天他。。。。。。。。。。。。。。。。。。。。。。。。。。挂了

作者: PRAM 时间: 2010-9-21 10:55
本帖最后由 PRAM 于 2010-9-21 11:05 编辑

xeon总会有一款要高一点的嘛

不过5270和5272还不够震撼
3.4G的5492才震撼嘛
对比9775
skywalker_hao 发表于 2010-9-21 10:12

电气性能和时钟频有必然关系？当年90NM P4 跑3.8G，现在45NM I7 3,4G，原来90NM比45NM性能还高啊

作者: PRAM 时间: 2010-9-21 10:57

某些专业网站认为45nm的shanghai有23-24个FO4延迟。而intel的penryn则是18-20个FO4延迟。penryn最 ...
spinup 发表于 2010-9-20 22:13

时钟频率由PLL决定

作者: PRAM 时间: 2010-9-21 11:00

一份半年前就应该人手一份的会议摘要被拿来当宝每天挤一点出来显眼
skywalker_hao 发表于 2010-9-21 10:03

你也可以把VLSI,IEDM,ISSCC,DAC,a-sscc,imec form的拿点出来让我们开开眼界

作者: PRAM 时间: 2010-9-21 11:11

某些专业网站认为45nm的shanghai有23-24个FO4延迟。而intel的penryn则是18-20个FO4延迟。penryn最 ...
spinup 发表于 2010-9-20 22:13

IBM的所谓SOI根本不像其FANS吹的这么神，下面就是明证--------------IBM
IBM SOI
IBM ASIC Flow
High
Can‟t Leverage
Only ASSP, no ASICs
Min 18 MonthsTSMC
Portable to any Fab
Large re-usable IP base with COT flow
Lower
Fully Leverage able
Full ASIC, ASSP capability
6-9 MonthsBenefits
• Time Revenue Reduced better 50%
• Cost Basis  Reduced by as much as 50%
• Opens new market , allows for new innovation
Core Ownership
Captive Fab
Limited IP
Cost Basis
port Mixed Signal IP
ASSP vs. ASICs
Development Cycle

作者: PRAM 时间: 2010-9-21 11:21

一份半年前就应该人手一份的会议摘要被拿来当宝每天挤一点出来显眼
skywalker_hao 发表于 2010-9-21 10:03

我现在就给你一个显眼的机会，DFM是什么意思？

作者: PRAM 时间: 2010-9-21 12:01

某些专业网站认为45nm的shanghai有23-24个FO4延迟。而intel的penryn则是18-20个FO4延迟。penryn最 ...
spinup 发表于 2010-9-20 22:13

拿一个不量产的东西吹有意义---------------------Molten silicon and atomic radiation are two of the hazards Intel is confronting in its race to make faster circuits, the company said on Friday at the International Electron Devices meeting in Washington DC.

As part of this battle it unveiled a new design for transistors, one of which it says will operate at speeds hundreds of times faster than today's production devices.

The terahertz transistor design -- a terahertz is a thousand gigahertz, or one trillion cycles a second -- is an evolution of current designs, using new materials such as zirconium dioxide. Smaller transistors go faster but also leak more current when turned off and need a higher voltage to work; zirconium dioxide is a superior insulator that reduces this leakage and thus reduces power consumption while maintaining speed and low voltages. Intel says that the new design will work down to around 0.6v before long.

Other problems tackled include high capacitance, which increases the power needed to turn the transistor on and slows it down, and radiation from the atmosphere and packaging, which injects electrons directly into the transistor and causes a "soft error" in memory or logic designs. These have been minimised by putting the transistor on a sheet of insulator, which shields the effects of the radiation.

It also reduces the amount of conductor present near the transistor thus reducing the capacitance. Intel's new design reduces the number of electrons left floating around after the transistor operates, making the design more consistent.

Pushing the frontiers of Moore's Law
Without these innovations, it would be extremely difficult to build Pro-Acessor with a billion transistors, which is predicted by Moore's Law to happen by 2007. That design will have 0.045u geometry, two-thirds smaller than that of today, and will operate at around a terahertz. If it weren't for the power reduction inherent in the new design, it could be expected to need around half a kilowatt per square centimetre, a power density higher than that in a nuclear reactor and one that would present a severe challenge to even the most ardent overclocker.

作者: PRAM 时间: 2010-9-21 12:02

根据这些数字如果amd的工艺只和intel相当，那shanghai连3g都应该爬不上........ ...
spinup 发表于 2010-9-20 22:13

The transistor drive current for AMD's 45-nm devices is much lower than that of the Intel HKMG transistors.不识字吗？

作者: dalao123 时间: 2010-9-21 14:22
技术贴要支持哦

作者: acqwer 时间: 2010-9-21 15:24

xeon总会有一款要高一点的嘛

不过5270和5272还不够震撼
3.4G的5492才震撼嘛
对比9775
skywalker_hao 发表于 2010-9-21 10:12

我以前只在贴吧看到小白认为65nm的Conroe最高只有3G是因为Intel只能做出3G的，没想到还有那么多“专家”也是这样想的，还把这个当论据来讨论intel的工艺。

作者: xf-108 时间: 2010-9-21 15:30
本帖最后由 xf-108 于 2010-9-21 15:33 编辑

当初AMD 65nm四核没出来的时候宣称核心面积只有150，最后出来都超过300了……难道这就是某饭声称AMD 65nm猫利率史上最高的原因？

作者: frankincense 时间: 2010-9-21 15:47
Athlon II X4核心面积也比Phenom II X4缩小了接近一半
然则从众多开核开L3的Athlon来看
AMD宁愿生产多一些大面积的Phenom也不想生产小面积的Athlon

作者: xf-108 时间: 2010-9-21 15:53
本帖最后由 xf-108 于 2010-9-21 16:01 编辑

Athlon II X4核心面积也比Phenom II X4缩小了接近一半
然则从众多开核开L3的Athlon来看
AMD宁愿生产多一些 ...
frankincense 发表于 2010-9-21 15:47

A2比P2就是少了L3部分，那部分成产成本应该是相对比较低的。
但是售价上面差得就比较多了。

按照某饭的计算，P2 X6面积高达346，良率低不少，成本是X4两倍多，但是价格定位却很低……

另外某饭估计的Lynnfield良率比Bloomfield低很多，成本高很多……真是杯具啊……

作者: PRAM 时间: 2010-9-21 16:08

A2比P2就是少了L3部分，那部分成产成本应该是相对比较低的。
但是售价上面差得就比较多了。

按照某饭 ...
xf-108 发表于 2010-9-21 15:53

intel利润率远高于AMD,不知道那些所谓FAN怎么解释

作者: acqwer 时间: 2010-9-21 16:12

当初AMD 65nm四核没出来的时候宣称核心面积只有150，最后出来都超过300了……难道这就是某饭声称AMD 65nm猫 ...
xf-108 发表于 2010-9-21 15:30

那人乱吹罢了，AMD最近几**利最高的是06Q1的59%，部分向65nm转型的Q3只有51%，Q4 Conroe发布之后就是一路走低了。

作者: xf-108 时间: 2010-9-21 16:13

intel利润率远高于AMD,不知道那些所谓FAN怎么解释
PRAM 发表于 2010-9-21 16:08

参见某饭定律：
AMD可以随意屏蔽核心廉价卖，说明了AMD 45nm生产成本非常低。
Clarkdale/Gulftown那么小核心居然卖那么高天价，说明了intel 32nm生产成本非常高，良率非常低。

作者: xf-108 时间: 2010-9-21 16:17
snb核心面积是否为4核225，双核150（传说比总面积195的clarkdale小22%）？
单核晶体管比nehalem多了那么多，L3还缩了，单核性能却没多少增长啊……
指令集部分占的面积真是越来越大了啊……

作者: Prescott 时间: 2010-9-21 17:49

The transistor drive current for AMD's 45-nm devices is much lower than that of the Intel HKMG t ...
PRAM 发表于 2010-9-21 12:02

问题是，有人认为越低越好的。

作者: spinup 时间: 2010-9-21 19:03
随意发了一帖，上线发现被追了5个回帖........

某些人的热情真叫人怕怕啊..........

作者: PRAM 时间: 2010-9-21 20:36

随意发了一帖，上线发现被追了5个回帖........

某些人的热情真叫人怕怕啊..........
spinup 发表于 2010-9-21 19:03

某些人什么都不知道，还写BLOG YY，佩服佩服

作者: spinup 时间: 2010-9-21 20:41

某些人什么都不知道，还写BLOG YY，佩服佩服
PRAM 发表于 2010-9-21 20:36

咱是外行。外行就不准yy了？

您老最nb，我认错行不？不该在您的地盘上发言的.......

作者: PRAM 时间: 2010-9-21 20:47

咱是外行。外行就不准yy了？

您老最nb，我认错行不？不该在您的地盘上发言的.......
spinup 发表于 2010-9-21 20:41

我怎么能和声称EOT越厚越好的牛人相比呢？

作者: spinup 时间: 2010-9-21 20:50

我怎么能和声称EOT越厚越好的牛人相比呢？
PRAM 发表于 2010-9-21 20:47

你自己再去读一遍。这句话有啥前提

顺便说一下，ibm的65 nm工艺用过1nm的Tox，就是说ibm在65nm技术实力赶上intel45nm了？

作者: PRAM 时间: 2010-9-21 20:58
quote]你自己再去读一遍。这句话有啥前提

顺便说一下，ibm的65 nm工艺用过1nm的Tox，就是说ibm在65nm技术实 ...
spinup 发表于 2010-9-21 20:50

[/quote]

这个其实不怎么好比较，因为双方的Vdd是不同的。不过请注意intel的 I off指标设在了400na/um。也就是说大大放宽了泄漏指标----intel 90nm时代prescott处理器饱受诟病的高功耗与此相互印证。另其Tox也缩小到了1.2nm，而据其他资料IBM/AMD此时的Tox维持在大约2.0nm， IBM/AMD的工艺相比intel优势是很明显的。经典啊，EOT越厚越好。蒋尚义，胡正明汗颜

作者: PRAM 时间: 2010-9-21 20:59
ibm的65 nmSOI的Tox是1，3NM

作者: PRAM 时间: 2010-9-21 21:02
本帖最后由 PRAM 于 2010-9-21 21:08 编辑

说到底我其实是一个“工艺控”因为最终决定处理器性能的就是工艺和规模。我一直偏向AMD是因为很早就知道在工艺方面AMD有一定的优势---虽然intel总是更早进入下一代工艺，I dsat指标也一直领先，但是我知道intel付出了怎样的代价。

这个帖子的内容其实与我以前写的不少文章有关，但那些文章并未普遍公开。不过现在关于工艺的科普文章越来越深入，敝帚自珍越来越没有意义了。这帖子就算给个小结。----------某人的自白，好像某人在NEW YORK 或者新竹，自己在R&D一样

作者: PRAM 时间: 2010-9-21 21:07
intel強悍的地方在於...它的45nm還是用dry lithography...

作者: acqwer 时间: 2010-9-21 21:13
嘉兰不是最喜欢算成本吗，就用上季度数据算算吧，销售额啊，市场占有率啊**利的数据都有，让大家看看看看AMD的成本优势到底“巨大”到什么程度。

作者: PRAM 时间: 2010-9-21 21:15

intel付出了怎样的代价------------1.不用昂贵的SOI，导致SOI现在用者寥寥无几 2.由於超越了光學臨近修正(OPC)和設計準則的範疇，英特爾的模型技術功能可以允許使用通常是落後一個世代的設備，來製造當代的晶片。這樣來說，不僅有較低成本的優勢並且允許使用現有設備來加速進展。以45奈米邏輯製程的關鍵層來說，根據Borodovsky所言，使用193奈米乾式微影取代浸潤式微影將可省下百分之27的成本。让别人的SOI无法普及，浸潤式微影出货量减少，代价太大了

作者: spinup 时间: 2010-9-21 21:22

quote]你自己再去读一遍。这句话有啥前提

顺便说一下，ibm的65 nm工艺用过1nm的Tox，就是说ibm在65nm技术 ...
PRAM 发表于 2010-9-21 20:58

有啥汗颜的？同样技术条件下更薄栅氧层栅场更强，同样工作电压下I dsat/ I off更理想。所以一般来说Tox更薄性能更好。可是有人就愿意牺牲I dsat和I off换更厚栅氧层有啥不可以？特别是此时I dsat也并不比对手差很多。

拿tsmc来是来现眼吗？更小的Tox却照样有更小的I dsat。同样I dsat/I off下谁更有优势还用说？
[attach]1388047[/attach]

作者: PRAM 时间: 2010-9-21 21:26
本帖最后由 PRAM 于 2010-9-21 21:29 编辑

对比一下INTEL 65 EOT 1.O CGP220,某公司所谓SOI有优势？

作者: PRAM 时间: 2010-9-21 21:28

有啥汗颜的？同样技术条件下更薄栅氧层栅场更强，同样工作电压下I dsat/ I off更理想。所以一般来 ...
spinup 发表于 2010-9-21 21:22

是啊，SUN，富士通真是BC，不用某公司的32NM SOI去用TSMC的28NM，某公司不是有所谓成本优势吗？

作者: PRAM 时间: 2010-9-21 21:28
http://rram.spaces.eepw.com.cn/-------这是我的BLOG

作者: spinup 时间: 2010-9-21 21:31

这是我的BLOG
PRAM 发表于 2010-9-21 21:28

老大您要显示您的英明神武用不着拿我这样一个外行来垫背吧？下次您的帖子我不回还不行吗？

作者: feilipu 时间: 2010-9-21 21:52
这个太高深了对一般人来说实在没有意义

作者: PRAM 时间: 2010-9-21 22:04
而IBM的power6使用了1.05nm的栅氧厚度，甚至比intel的都小。--------------INTEL 65是 EOT 1.O,某人无敌

作者: PRAM 时间: 2010-9-21 22:07

有啥汗颜的？同样技术条件下更薄栅氧层栅场更强，同样工作电压下I dsat/ I off更理想。所以一般来以一般来说Tox更薄性能更好。spinup 发表于 2010-9-21 21:22

32nm阶段：

IBM/AMD首次使用dual pattern的曝光模式和HKMG。这两者都是相当“昂贵”的，而且不可避免。
注意“浸入式曝光”和“双曝光模式”都是可以使193nm刻更细的线的技术，有趣的是IBM/AMD和intel使用的次序恰相反，只是32nm下将殊途同归。

IBM/AMD的I dsat参数仅略逊于intel(考虑到AC-DC折算)，但是EOT却大了不少，所以就性能而言，IBM/AMD公布的数据将有明显优势。如果gate first确实能降低成本，则IBM/AMD可能还有一些成本优势。
--------------一个人说的话，意思完全相反

作者: PRAM 时间: 2010-9-21 22:08
本帖最后由 PRAM 于 2010-9-21 22:11 编辑

有啥汗颜的？同样技术条件下更薄栅氧层栅场更强，同样工作电压下I dsat/ I off更理想。所以一般来所以一般来说Tox更薄性能更好 ...
spinup 发表于 2010-9-21 21:22

130nm下intel的Idsat参数明显好一些（大约20%），但是Tox却小了近50%----也就是说同样栅面积电容要大50%，所以综合性能其实还是会略逊的。 ----阁下真是雄辩，前后意思完全相反，不知道还有逻辑吗？

作者: PRAM 时间: 2010-9-21 22:10
要注意IBM/AMD的一些关键参数如EOT都是相当保守的，实际上AMD是以保守工艺应对intel的同代工艺，而以改进后的工艺应对intel的下一代工艺，所以intel并不能明显地拉开差距。保守的工艺好处是代价小，这就是AMD一直能保持对intel性价比优势的根本原因。--------阁下难道不知道，工艺和DESIGN 是密不可分的，能轻易改变？何况AMD也不存在所谓性价比优势

作者: PRAM 时间: 2010-9-21 22:19
要注意IBM/AMD的一些关键参数如EOT都是相当保守的，实际上AMD是以保守工艺应对intel的同代工艺，而以改进后的工艺应对intel的下一代工艺，所以intel并不能明显地拉开差距。保守的工艺好处是代价小，这就是AMD一直能保持对intel性价比优势的根本原因=======阁下的说法和GF,TSMC,HYNIX所有的R&D人员都不同，真理果然掌握在阁下这样的少数人手中

作者: rtyou 时间: 2010-9-21 22:21
还好有懂的人，我差点让某人忽悠到“AMD的制程比Intel还先进”这个高级笑话。

作者: PRAM 时间: 2010-9-21 22:23
INTEL的成本控制要遥遥领先于IBM，一方面，制程演进可以直接压缩DIE面积，另一方面，INTEL在技术实现上的务实态度也让它在单位晶圆成本表现上强于IBM

作者: spinup 时间: 2010-9-21 22:30

130nm下intel的Idsat参数明显好一些（大约20%），但是Tox却小了近50%----也就是说同样栅面积电容要大50 ...
PRAM 发表于 2010-9-21 22:08

要是ibm用的技术和intel一模一样，仅仅是栅氧厚度增加50%会发生什么情况？
个人猜测要么I dsat小到可笑，要不I off大到可笑。问题是ibm就能做到用这么大的栅氧厚度但是I dsat和 I off都不算可笑。“As discussed in one of David Wang's first articles on IEDM, the Cgate * Vdd / Idsat metric is used as Pro-Acess neutral” 用这个衡量I小了一点，但是C小了很多。

似乎我的小学算术还没忘光，不小心算出一个ibm性能占优的结果了？.....可是数据都是techreport提供的啊。您老大能量大，叫他们改正错误，我这里马上改。

作者: PRAM 时间: 2010-9-21 22:32
本帖最后由 PRAM 于 2010-9-21 22:35 编辑

某人一会说是IBM的PMOS,NMOS性能不如INTEL,EOT却大了不少，所以就性能而言，IBM/AMD公布的数据将有明显优势，一会儿有说Tox更薄性能更好。可是有人就愿意牺牲I dsat和I off换更厚栅氧层有啥不可以？特别是此时I dsat也并不比对手差很多。----某人相信雄辩胜于事实

作者: PRAM 时间: 2010-9-21 22:32
一个PMOS,NMOS性能不如INTEL，EOT却大了不少的所谓32NM SOI会有优势

作者: jwlili1 时间: 2010-9-21 22:32
说了这么多，结论是ibm更强？还是intel更厉害？没看懂

作者: PRAM 时间: 2010-9-21 22:37

要是ibm用的技术和intel一模一样，仅仅是栅氧厚度增加50%会发生什么情况？
个人猜测要么I dsat小到可笑 ...
spinup 发表于 2010-9-21 22:30

是INTEL的EOT更小啊，是啊INTEL栅氧厚度增加50%会发生什么情况？

作者: PRAM 时间: 2010-9-21 22:41

要是ibm用的技术和intel一模一样，仅仅是栅氧厚度增加50%会发生什么情况？
个人猜测要么I dsat小到可笑 ...
spinup 发表于 2010-9-21 22:30

http://techreport.com/这种网站你好意思吹，我看EET,NMD,SI,SST

作者: spinup 时间: 2010-9-21 22:44

这种网站你好意思吹，我看EET,NMD,SI,SST
PRAM 发表于 2010-9-21 22:41

咱是外行，只能看这些外行网站。不过他们数据是copy正式会议的信息，算法也是专家给的-------看来一定是这种小网站copy时候copy错了。

作者: PRAM 时间: 2010-9-21 22:47
本帖最后由 PRAM 于 2010-9-21 22:50 编辑

要是ibm用的技术和intel一模一样，仅仅是栅氧厚度增加50%会发生什么情况？
个人猜测要么I dsat小到可笑 ...
spinup 发表于 2010-9-21 22:30

是谁的EOT小阁下没看清楚？

作者: PRAM 时间: 2010-9-21 22:51

咱是外行，只能看这些外行网站。不过他们数据是copy正式会议的信息，算法也是专家给的 ...
spinup 发表于 2010-9-21 22:44

不是数据有问题，是谁的EOT小阁下没看清楚

作者: PRAM 时间: 2010-9-21 22:53
IBM强大的都是纸面技术,特許、聯電這批抱IBM大腿的這幾年都被tsmc打得快下海賣身了，更何況有NV多年前給IBM代工的慘痛經驗
，很奇怪不少人喜欢神话IBM，在半导体芯片生产上IBM比intel差十万八千里,IBM的某神话芯片，被用在某游戏机上的，开发团队也正式解散了

作者: spinup 时间: 2010-9-21 22:54

所谓外行就是阁下
PRAM 发表于 2010-9-21 22:47

在下不是已经说了很多次了？在下只会一点小学算术，不小心把ibm的废物工艺算得比intel强大工艺还高了那么一点点，望大人不计小人过，放过在下，去讨伐techreport误导我等外行为宜。

作者: PRAM 时间: 2010-9-21 22:56

咱是外行，只能看这些外行网站。不过他们数据是copy正式会议的信息，算法也是专家给的 ...
spinup 发表于 2010-9-21 22:44

IBM technology is better than TSMC. However, in the production condition, TSMC is more discipline company; IBM, a research oriented company. Intel discipline is more tough than TSMC. 读不懂这句话的话，请继续YY

作者: 深谷白云 时间: 2010-9-21 22:57
本帖最后由深谷白云于 2010-9-21 22:59 编辑

intel的新神话芯片larrabee又如何了？

，被用在了那里？

作者: PRAM 时间: 2010-9-21 22:59

在下不是已经说了很多次了？在下只会一点小学算术，不小心把ibm的废物工艺算得比intel强大工艺还高了 ...
spinup 发表于 2010-9-21 22:54

一会说是IBM的PMOS,NMOS性能不如INTEL,EOT却大了不少，所以就性能而言，IBM/AMD公布的数据将有明显优势，一会儿有说Tox更薄性能更好。可是有人就愿意牺牲I dsat和I off换更厚栅氧层有啥不可以？特别是此时I dsat也并不比对手差很多。----这跟小学算术没有关系，是前后逻辑有问题

作者: the_god_of_pig 时间: 2010-9-21 23:02

intel的新神话芯片larrabee又如何了？，被用在了那里？
深谷白云发表于 2010-9-21 22:57

插不上话的可怜人路过

作者: PRAM 时间: 2010-9-21 23:02

intel的新神话芯片larrabee又如何了？，被用在了那里？
深谷白云发表于 2010-9-21 22:57

larrabee改为MIC了

作者: 深谷白云 时间: 2010-9-22 00:17

插不上话的可怜人路过
the_god_of_pig 发表于 2010-9-21 23:02

对半导体工艺完全不懂……

作者: Jason21 时间: 2010-9-22 09:47
技术贴，原来之前一直被某人忽悠了

作者: PRAM 时间: 2010-9-22 09:51

在下不是已经说了很多次了？在下只会一点小学算术，不小心把ibm的废物工艺算得比intel强大工艺还高了 ...
spinup 发表于 2010-9-21 22:54

-阁下所依赖的techreport的结论-------------
The semiconductor industry is gearing up for a 32nm battle royale, with Intel, IBM, GlobalFoundries, TSMC, and others all prepping competing technologies at the same node. How will they match up? Fresh from the 2008 International Electron Devices Meeting and the 2009 VLSI Symposia, David Kanter of Real World Technologies has posted an in-depth article that seeks to answer that question.

Kanter's comparison includes IBM's high-k metal gate (HKMG) 32nm bulk and silicon-on-insulator processes, which GlobalFoundries should use to manufacture chips for AMD next year. The article also examines TSMC's performance 32nm HKMG process, which should be used to make future graphics processors, and Intel's performance HKMG tech, which we'll see in Clarkdale processors either late this year or in early 2010.

Now, some parts of this piece will probably be well over most readers' heads—unless they happen to have electrical engineering or semiconductor design backgrounds, that is, in which case we expect them to nod their heads slowly and go, "Hmm, yes, very interesting." How else do you expect seasoned engineers to react to graphs like these?

The rest of us might want to skip ahead to page 11, which includes a more accessible and quite interesting overview of the aforementioned processes (plus others from TI and Fujitsu). Here, Kanter comments that IBM's 32nm SOI and Intel's 32nm bulk technologies "have the best transistor performance by a wide margin and with almost identical results." He adds, "This suggests that on paper, Intel, IBM and AMD will be at parity for performance. Although Intel will be in production in late 2009, a year ahead of IBM and AMD."
Kanter makes other interesting observations. Intel's current 45nm process is "ahead of all other production processes," including TSMC's bulk 32nm process. Also, IBM's 32nm bulk process is "closely matched" with TSMC's. That means competition between GlobalFoundries and TSMC at the 32nm node may be quite heated.

作者: PRAM 时间: 2010-9-22 09:53
要注意的是， IBM's 32nm SOI and Intel's 32nm bulk technologies "have the best transistor performance by a wide margin and with almost identical results指的是INTEL 2008IEDM发表的32NM和IBM 2009年发表的32NM性能相当，INTEL IEDM2009发表的32NM性能又有提升

作者: PRAM 时间: 2010-9-22 09:55

在下不是已经说了很多次了？在下只会一点小学算术，不小心把ibm的废物工艺算得比intel强大工艺还高了 ...
spinup 发表于 2010-9-21 22:54

阁下可以带领国内正在立项的32/22NM项目了

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