标题: HASWELL UPDATE [打印本页] 作者: PRAM 时间: 2011-1-21 14:50 标题: HASWELL UPDATE Haswell is expected to have the following features:[1][4]
22 nm process.
14 stage pipeline.
Up to 8 cores by default.
An entirely new cache design.
Advanced power saving mechanisms.
Possible on-package vector coprocessors.
The addition of fused multiply-add (FMA) instructions.
There is a chance that it will be designed for DDR4 as production timings are quite close to each other.
128 kb L1 cache per core (64 kb data + 64 kb instruction), 4-way associativity.
1 MB L2 cache per core, 4-way associativity.
Up to 16 MB L3 cache shared by all cores, 8-way associativity. 作者: 000000yyy 时间: 2011-1-21 14:54
这是哪国文字作者: kinno 时间: 2011-1-21 16:50
默认就8核心，全新的缓存设计，值得期待啊作者: amd```fans 时间: 2011-1-21 17:18
8 cores那是Up to 8 cores by default吧
只能说有默认8核的可能性作者: zaknafein 时间: 2011-1-21 17:42
有种一年前就看过了的感觉作者: Edison 时间: 2011-1-21 17:56
wiki 上的啦。作者: the_god_of_pig 时间: 2011-1-21 18:39
YY的吧..作者: jason_sean 时间: 2011-1-21 20:07
缓存和INTEL以往不大对路哦 全新设计？作者: 李主任 时间: 2011-1-21 20:09
