标题: 9260-8i uart得到的信息,求有弄过的指点! [打印本页] 作者: coldcoffee 时间: 2014-5-7 01:03 标题: 9260-8i uart得到的信息,求有弄过的指点! [attach]2559822[/attach]
[attach]2559823[/attach]
通过COM口得到一些启动过程,其中有多处有
Press '!' within 3 seconds to enter debugger before INIT
但是按了!也没用,或者是有其它的方法进入,希望有调试过的朋友指点指点
作者: coldcoffee 时间: 2014-5-7 01:09
本次启动完整过程,中间没做任何操作,不过与前几次想比,有些是重复的,不知何故,看过TTYlog的很眼熟,呵呵
T0: MEM_POOL_BASE: 84368cd8
T0: Initializing memory pool size=01497328 bytes
T0: Press '!' within 3 seconds to enter debugger before INIT
LSI Logic Boot loader
LSI ROC initialization code
VID 1000 DID 79 SSVID 1000 SSID 9261 Rev 05
Frequencies: CPU: 800 Mhz, PLB: 200 Mhz, DDR: 400 Mhz
SysRstSns 80000001 PceMiscCfg 0091c600 PceCfgValid 00000001
SysPllCtrl 8032f561 MemPllCtrl 8030f561
I2C 0 reset!
Mem Dll lock took 11 us
I2C 0 reset!
>> SPD data begin <<
Memory Type: DDR-2
Memory Speed: 400 Mhz [2.50ns]
Data Width: 72 bits
#RAS Bits: 13
#CAS Bits: 10
#Banks each chip: 8
Chip width: x16
#Banks in DIMM: 1
DIMM Size: 512MB (1024MB calculated from other SPD data)
CAS Latency: CL3, CL4, CL5, CL6,
Registered: No
Voltage Standard: SSTL 1.8
DIMM Config Type: ECC
SPD Checksum: 0x27 (checksum is Good)
>> SPD data end <<
RAW SPD Data:
00000000: 80 08 08 0d 0a 00 48 00 - 05 25 40 02 82 10 08 00
00000010: 0c 08 78 00 00 00 03 30 - 45 3d 50 3c 28 3c 2d 80
00000020: 17 25 05 12 3c 1e 1e 00 - 06 3c 7f 80 14 1e 00 00
00000030: 00 03 00 00 00 00 00 00 - 00 00 00 00 00 00 13 27
initDDR: SBR is configured for a speed below capabilities of installed DIMM
******** Board = 800 Mhz, DIMM supports 800 Mhz
using CasLat 6
DDR init sequence completed in b us
fifoDelayIndex = 7
gateon[0] complete. 0=8f, 1=92, 2=91, 3=91, 4=8f, 5=91, 6=8f, 7=8f,
gateon[1] complete. 8=8d,
All bytes failed dec. current: e0
fifo Train(Ecc) failed Bytes 0
fifo Train(Ecc) ecc pat failed Bytes 100
fifo Train(Ecc) test 2 ecc pat failed Bytes 0
Fifo training completed. rdqs 000 delays: 0=a0 1=a0 2=a0 3=a0 4=a0 5=a0 6=a0 7=a0 8=a0
init ReadEye training dataorEcc 0
ReadEye edge 0 Results
Nib base Low High Avg
00 0054 ffffffca 0027 fffffff9
01 0056 ffffffca 0029 fffffffa
02 0056 ffffffc7 0029 fffffff8
03 0054 ffffffcd 002a fffffffc
04 0054 ffffffc6 0029 fffffff8
05 0057 ffffffcb 002a fffffffb
06 0053 ffffffc3 002d fffffff8
07 0056 ffffffcb 0031 fffffffe
08 0052 ffffffcc 002a fffffffb
09 0055 ffffffc9 0026 fffffff8
0a 0053 ffffffca 002a fffffffa
0b 0056 ffffffca 0024 fffffff7
0c 0053 ffffffc9 002a fffffffa
0d 0055 ffffffc9 002a fffffffa
0e 0056 ffffffc4 002a fffffff7
0f 0058 ffffffc8 002a fffffff9
ReadEye edge 1 Results
Nib base Low High Avg
00 0050 ffffffcb 0025 fffffff8
01 0056 ffffffc4 0026 fffffff5
02 0050 ffffffcb 0026 fffffff9
03 0057 ffffffcd 002a fffffffc
04 0052 ffffffca 0026 fffffff8
05 0055 ffffffcb 002a fffffffb
06 0054 ffffffc8 0026 fffffff7
07 0057 ffffffcb 002a fffffffb
08 004d ffffffcc 0023 fffffff8
09 0056 ffffffc5 0023 fffffff4
0a 004d ffffffcb 0026 fffffff9
0b 0056 ffffffcb 002a fffffffb
0c 004f ffffffc9 0026 fffffff8
0d 0056 ffffffca 0026 fffffff8
0e 0051 ffffffc6 0027 fffffff7
0f 0057 ffffffc8 002d fffffffb
init ReadEye training dataorEcc 1
ReadEye edge 0 Results
Nib base Low High Avg
10 0054 ffffffc9 0028 fffffff9
11 0055 ffffffc9 0028 fffffff9
ReadEye edge 1 Results
Nib base Low High Avg
10 004e ffffffca 0025 fffffff8
11 0054 ffffffca 0025 fffffff8
Second run of FIFO Delay training.
All bytes failed dec. current: e0
fifo Train(Ecc) failed Bytes 0
fifo Train(Ecc) ecc pat failed Bytes 100
fifo Train(Ecc) test 2 ecc pat failed Bytes 0
Fifo training completed. rdqs 000 delays: 0=a0 1=a0 2=a0 3=a0 4=a0 5=a0 6=a0 7=a0 8=a0
Done
Dirty DRAM signature not found.. Cache is not dirty
Verifying TTY history log [addr=0x80100000, 1 MB]: Done
Testing memory [addr=0x0, 1 MB]: Done
Testing memory [addr=0x200000, 510 MB]: Done
SramSignature 0
Scrubbing between DramPersistent and TTY [addr=0x80040000-0x80100000]
loadBios: Images found=3 start=80040000 size=12a00
Scrubbing DramPersistent [addr=0x80000000-0x80040000]
Scrubbing from end of TTY to Disk Cache [addr=0x80200000-0x85800000]
Scrubbing Disk Cache [addr=0x85800000, 424 MB]
T0: LSI ROC firmware
T0: Copyright(C) LSI Corporation, 2010
T0: Firmware version 2.120.183-1415 built on Oct 5 2011 at 12:32:12
T0: *** HW Encryption Disabled : dcrReg=80000001
T0: setAdapterResetTime: CCR_MISC_CFG 8002ff2c
T0: DRAM_LOCAL_BASE: 80000000
T0: MEM_FIXED_SIZE: a00000
T0: FW_DRAM_REGION_START: 80c00000
T0: FW_DRAM_REGION_SIZE: 4c00000
T0: MEM_POOL_BASE: 84368cd8
T0: Initializing memory pool size=01497328 bytes
T0: Press '!' within 3 seconds to enter debugger before INIT
LSI Logic Boot loader
LSI ROC initialization code
VID 1000 DID 79 SSVID 1000 SSID 9261 Rev 05
Frequencies: CPU: 800 Mhz, PLB: 200 Mhz, DDR: 400 Mhz
SysRstSns 80000001 PceMiscCfg 0091c600 PceCfgValid 00000001
SysPllCtrl 8032f561 MemPllCtrl 8030f561
I2C 0 reset!
Mem Dll lock took 10 us
I2C 0 reset!
>> SPD data begin <<
Memory Type: DDR-2
Memory Speed: 400 Mhz [2.50ns]
Data Width: 72 bits
#RAS Bits: 13
#CAS Bits: 10
#Banks each chip: 8
Chip width: x16
#Banks in DIMM: 1
DIMM Size: 512MB (1024MB calculated from other SPD data)
CAS Latency: CL3, CL4, CL5, CL6,
Registered: No
Voltage Standard: SSTL 1.8
DIMM Config Type: ECC
SPD Checksum: 0x27 (checksum is Good)
>> SPD data end <<
RAW SPD Data:
00000000: 80 08 08 0d 0a 00 48 00 - 05 25 40 02 82 10 08 00
00000010: 0c 08 78 00 00 00 03 30 - 45 3d 50 3c 28 3c 2d 80
00000020: 17 25 05 12 3c 1e 1e 00 - 06 3c 7f 80 14 1e 00 00
00000030: 00 03 00 00 00 00 00 00 - 00 00 00 00 00 00 13 27
initDDR: SBR is configured for a speed below capabilities of installed DIMM
******** Board = 800 Mhz, DIMM supports 800 Mhz
using CasLat 6
DDR init sequence completed in b us
fifoDelayIndex = 7
gateon[0] complete. 0=8f, 1=91, 2=91, 3=91, 4=91, 5=91, 6=8f, 7=8f,
gateon[1] complete. 8=8d,
All bytes failed dec. current: e0
fifo Train(Ecc) failed Bytes 0
fifo Train(Ecc) ecc pat failed Bytes 100
fifo Train(Ecc) test 2 ecc pat failed Bytes 0
Fifo training completed. rdqs 000 delays: 0=a0 1=a0 2=a0 3=a0 4=a0 5=a0 6=a0 7=a0 8=a0
init ReadEye training dataorEcc 0
ReadEye edge 0 Results
Nib base Low High Avg
00 0055 ffffffcc 0026 fffffff9
01 0054 ffffffcb 002d fffffffc
02 0057 ffffffc5 0026 fffffff6
03 0054 ffffffcd 002c fffffffd
04 0054 ffffffc6 0029 fffffff8
05 0056 ffffffcc 0029 fffffffb
06 0054 ffffffc2 002c fffffff7
07 0056 ffffffcb 002c fffffffc
08 0054 ffffffcc 0025 fffffff9
09 0054 ffffffca 0023 fffffff7
0a 0054 ffffffc6 002a fffffff8
0b 0055 ffffffcc 0026 fffffff9
0c 0054 ffffffc9 0029 fffffff9
0d 0054 ffffffca 0029 fffffffa
0e 0057 ffffffc3 0029 fffffff6
0f 0057 ffffffc9 0029 fffffff9
ReadEye edge 1 Results
Nib base Low High Avg
00 0050 ffffffcd 0025 fffffff9
01 0056 ffffffc4 0028 fffffff6
02 0051 ffffffcc 0028 fffffffa
03 0057 ffffffcd 0029 fffffffb
04 0051 ffffffcb 0029 fffffffa
05 0056 ffffffcc 0028 fffffffa
06 0052 ffffffc7 0029 fffffff8
07 0057 ffffffcb 002c fffffffc
08 004b ffffffcd 0022 fffffff8
09 0056 ffffffc5 0025 fffffff5
0a 004e ffffffcb 0022 fffffff7
0b 0057 ffffffcc 0029 fffffffb
0c 004e ffffffca 0028 fffffff9
0d 0056 ffffffca 0028 fffffff9
0e 0050 ffffffc7 0028 fffffff8
0f 0058 ffffffc9 002c fffffffb
init ReadEye training dataorEcc 1
ReadEye edge 0 Results
Nib base Low High Avg
10 0055 ffffffca 0025 fffffff8
11 0055 ffffffca 0025 fffffff8
ReadEye edge 1 Results
Nib base Low High Avg
10 004d ffffffca 0025 fffffff8
11 0053 ffffffca 0025 fffffff8
Second run of FIFO Delay training.
All bytes failed dec. current: e0
fifo Train(Ecc) failed Bytes 0
fifo Train(Ecc) ecc pat failed Bytes 100
fifo Train(Ecc) test 2 ecc pat failed Bytes 0
Fifo training completed. rdqs 000 delays: 0=a0 1=a0 2=a0 3=a0 4=a0 5=a0 6=a0 7=a0 8=a0
Done
Dirty DRAM signature not found.. Cache is not dirty
Verifying TTY history log [addr=0x80100000, 1 MB]: Done
Testing memory [addr=0x0, 1 MB]: Done
Testing memory [addr=0x200000, 510 MB]: Done
SramSignature 0
Scrubbing between DramPersistent and TTY [addr=0x80040000-0x80100000]
loadBios: Images found=3 start=80040000 size=12a00
Scrubbing DramPersistent [addr=0x80000000-0x80040000]
Scrubbing from end of TTY to Disk Cache [addr=0x80200000-0x85800000]
Scrubbing Disk Cache [addr=0x85800000, 424 MB]