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标题: Intel发布Conroe已知Bug列表 [打印本页]

作者: wodeer2003 时间: 2006-8-26 12:38
标题: Intel发布Conroe已知Bug列表
Intel公司最近在其网站发布了一份PDF文档，公布了代号“Conroe”的Core 2 Extreme和Core 2 Duo处理器的已知Bug。

文档包含了已经明确的67个处理器Bug，指出了他们的故障环境和表现。半数以上的Bug处在“Not Fix”的未修正状态，其他则为计划修正。不过不用担心，几乎所有的处理器在发售之初都会有这样那样的问题，随着CPU制程的更换，大部分都可以得到修正。并且除了代号AI 39的问题被Intel警告可能导致系统崩溃外，大部分的Bug在一般使用中都不会被察觉。

可以到这里下载这篇技术文档

作者: ppzhong 时间: 2006-8-26 13:04
K8现在都还有130多个BUG未搞定........

作者: 珊瑚虫虫 时间: 2006-8-26 13:05

原帖由 ppzhong 于 2006-8-26 13:04 发表
K8现在都还有130多个BUG未搞定........

哪130个？

作者: Songhaipeng 时间: 2006-8-26 13:10
等段时间考虑扣肉，等 intel 捉完嗅虫再买

作者: 下午开船 时间: 2006-8-26 13:16
谁给翻译一下吧

作者: TZ-Gerald 时间: 2006-8-26 13:23
只要不影响使用我就不理它了……

作者: yoyofuture88 时间: 2006-8-26 13:29
停电当机的机率更大些.

作者: Illuminati 时间: 2006-8-26 13:54
Prescott 核心直到 E0 版为止还有 80 多个 bug，每一个新 stepping 去掉了一部分 bug，同时引入新的 bug

这些无知小便这种事也拿来炒作，没有一个市面上的 CPU 有 < 50 的 bug，要是等，等到 Conroe 退伍也不会除尽的，别被忽悠了

NO. C01 D0 LD02 E0 LE02 Plan ERRATA
R1 X X X X X No Fix Transaction Is Not Retried after BINIT#
R2 X X X X X No Fix Invalid Opcode 0FFFh Requires a ModRM Byte
R3 X X X X X No Fix Processor May Hang Due to Speculative Page Walks to Non-
Existent System Memory
R4 X X X X X No Fix Memory Type of the Load Lock Different from Its Corresponding
Store Unlock
R5 X X X X X No Fix Machine Check Architecture Error Reporting and Recovery May
Not Work As Expected
R6 X X X X X No Fix Debug Mechanisms May Not Function as Expected
R7 X X X X X No Fix Cascading of Performance Counters Does Not Work Correctly
When Forced Overflow Is Enabled
R8 X X X X X No Fix EMON Event Counting of x87 Loads May Not Work As
Expected
R9 X X X X X No Fix System Bus Interrupt Messages without Data Which Receive a
HardFailure Response May Hang the Processor
R10 X X X X X No Fix
The Processor Signals Page-Fault Exception (#PF) Instead of
Alignment Check Exception (#AC) on an Unlocked
CMPXCHG8B Instruction
R11 X X X X X No Fix FSW May Not Be Completely Restored after Page Fault on
FRSTOR or FLDENV Instructions
R12 X X X X X No Fix Processor Issues Inconsistent Transaction Size Attributes for
Locked Operation
R13 X X X X X No Fix When the Processor Is in the System Management Mode
(SMM), Debug Registers May Be Fully Writeable
R14 X X X X X No Fix Shutdown and IERR# May Result Due to a Machine Check
Exception on a Hyper-Threading Technology Enabled Processor
R15 X X X X X No Fix Processor May Hang under Certain Frequencies and 12.5%
STPCLK# Duty Cycle
R16 X X X X X No Fix
System May Hang if a Fatal Cache Error Causes Bus Write Line
(BWL) Transaction to Occur to the Same Cache Line Address
as an Outstanding Bus Read Line (BRL) or Bus Read-Invalidate
Line (BRIL}
R17 X X X X X No Fix A Write to APIC Registers Sometimes May Appear to Have Not
Occurred
R18 X Fixed Some Front Side Bus I/O Specifications are not Met
R19 X X X X X No Fix Parity Error in the L1 Cache May Cause the Processor to Hang
R20 X Fixed BPM4# Signal Not Being Asserted According to Specification
R21 X X X X X No Fix Sequence of Locked Operations Can Cause Two Threads to
Receive Stale Data and Cause Application Hang
R22 X X X Fixed
A 16-bit Address Wrap Resulting from a Near Branch (Jump or
Call) May Cause an Incorrect Address to be Reported to the
#GP Exception Handler
R23 X X X X X No Fix Bus Locks and SMC Detection May Cause the Processor to
Hang Temporarily
R24 X Fixed PWRGOOD and TAP Signals Maximum Input Hysteresis Higher
Than Specified
R25 X X X Fixed Incorrect Physical Address Size Returned by CPUID Instruction
R26 X X X X X No Fix Incorrect Debug Exception (#DB) May Occur When a Data
Breakpoint is set on an FP Instruction
R27 X X X X X No Fix xAPIC May Not Report Some Illegal Vector Errors
R28 X X X X X Plan Fix
Enabling No-Eviction Mode (NEM) May Prevent the Operation of
the Second Logical Processor in a Hyper-Threading Technology
Enabled Processor
R29 X X X X X No Fix
Incorrect Duty Cycle is Chosen when On-Demand Clock
Modulation is Enabled in a Processor Supporting Hyper-
Threading Technology
R30 X X X X X No Fix Memory Aliasing of Pages as Uncacheable Memory Type and
Write Back (WB) May Hang the System
R31 X X X X X Plan Fix
Interactions Between the Instruction Translation Lookaside
Buffer (ITLB) and the Instruction Streaming Buffer May Cause
Unpredictable Software Behavior
R32 X X X Fixed STPCLK# Signal Assertion under Certain Conditions May Cause
a System Hang
R33 X Fixed Missing Stop Grant Acknowledge Special Bus Cycle May Cause
a System Hang
R34 X Fixed Changes to CR3 Register do not Fence Pending Instruction
Page Walks
R35 X Fixed
Simultaneous Page Faults at Similar Page Offsets on Both
Logical Processors of an Hyper-Threading Technology Enabled
Processor May Cause Application Failure
R36 X Fixed The State of the Resume Flag (RF Flag) in a Task-State
Segment (TSS) May be Incorrect
R37 X X X X X No Fix Using STPCLK and Executing Code From Very Slow Memory
Could Lead to a System Hang
R38 X X X X X No Fix Processor Provides a 4-Byte Store Unlock After an 8-Byte Load
Lock
R39 X X X X X No Fix Data Breakpoints on the High Half of a Floating Point Line Split
may not be Captured
R40 X Fixed CPUID Instruction May Report Incorrect L2 Associativity in Leaf
0x80000006
R41 X Fixed The FP_ASSIST EMON Event May Return an Incorrect Count
R42 X X X X X No Fix Machine Check Exceptions May not Update Last-Exception
Record MSRs (LERs)
R43 X X X X X No Fix MOV CR3 Performs Incorrect Reserved Bit Checking When in
PAE Paging
R44 X X X X X No Fix
Stores to Page Tables May Not Be Visible to Pagewalks for
Subsequent Loads Without Serializing or Invalidating the Page
Table Entry
R45 X X X X Plan Fix Execution of IRET or INTn Instructions
May Cause Unexpected System Behavior
R46 X X X Fixed A Split Store Memory Access May Miss a Data Breakpoint
R47 X X Fixed EFLAGS.RF May be Incorrectly Set After an IRET Instruction
R48 X Fixed Read for Ownership and Simultaneous Fetch May Cause the
Processor to Hang
R49 X X Fixed Writing the Echo TPR Disable Bit in IA32_MISC_ENABLE May
Cause a #GP Fault
R50 X Fixed Cache Lock with Simultaneous Invalidate external snoop and
SMC check May Cause the Processor to Hang
R51 X Fixed IRET Instruction Performing Task Switch May Not Serialize the
Processor Execution
R52 X X X Fixed Incorrect Access Controls to
MSR_LASTBRANCH_0_FROM_LIP MSR Registers
R53 X X X X No Fix Recursive Page Walks May Cause a System Hang
R54 X5 X X Fixed
WRMSR to bit[0] of IA32_MISC_ENABLE Register Changes
Only One Logical Processor on a Hyper-Threading Technology
Enabled Processor
R55 X3,5 X3,5 Plan Fix VERR/VERW Instructions May Cause #GP Fault when
Descriptor is in Non-canonical Space
R56 X3 X3 Plan Fix
The Base of a Null Segment May be Non-zero on a Processor
Supporting Intel® Extended Memory 64 Technology (Intel®
EM64T) Φ
R57 X3 X3 Plan Fix
Upper 32 Bits of FS/GS with Null Base May not get Cleared in
Virtual-8086 Mode on Processors with Intel® Extended Memory
64 Technology (Intel® EM64T) Enabled
R58 X3 X3 No Fix
Processor May Fault when the Upper 8 Bytes of Segment
Selector is Loaded From a Far Jump Through a Call Gate via the
Local Descriptor Table
R59 X3 X3 No Fix
Loading a Stack Segment with a Selector that References a
Non-canonical Address can Lead to a #SS Fault on a Processor
Supporting Intel® Extended Memory 64 Technology (Intel®
EM64T)
R60 X3 X3 No Fix
FXRSTOR May Not Restore Non-canonical Effective Addresses
on Processors with Intel® Extended Memory 64 Technology
(Intel® EM64T) Enabled
R61 X3 X3 No Fix A Push of ESP that Faults may Zero the Upper 32 Bits of RSP
R62 X Plan Fix
Enhanced Halt State (C1E) Voltage Transition May Affect a
System’s Power Management in a Hyper-Threading Technology
Enabled Processor
R63 X No Fix Enhanced Halt State (C1E) May Not Be Entered in a Hyper-
Threading Technology Enabled Processor
R64 X Plan Fix When the Execute Disable Bit Function is Enabled a Page-fault
in a Mispredicted Branch May Result in a Page-fault Exception
R65 X Plan Fix Execute Disable Bit Set with AD Assist Will Cause Livelock
R66 X Plan Fix The Execute Disable Bit Fault May be Reported Before Other
Types of Page Fault When Both Occur
R67 X Plan Fix Writes to IA32_MISC_ENABLE May Not Update Flags for Both
Logical Processors Threads
R68 X Plan Fix Execute Disable Mode may Cause Livelock
R69 X X X X X No Fix Checking of Page Table Base Address May Not Match the
Address Bit Width Supported by the Platform
R70 X X X X X No Fix The IA32_MCi_STATUS MSR May Improperly Indicate that
Additional MCA Information May Have Been Captured
R71 X Fixed
Execution of an Instruction with a Code Breakpoint Inhibited by
the RF (Resume Flag) Bit May be Delayed by an RFO (Request
For Ownership) from Another Bus Agent
R72 X X X X X No Fix
With TF (Trap Flag) Asserted, FP Instruction That Triggers an
Unmasked FP Exception May Take Single Step Trap Before
Retirement of Instruction
R73 X X X Fixed MCA Corrected Memory Hierarchy Error Counter May Not
Increment Correctly
R74 X X X X X No Fix BTS(Branch Trace Store) and PEBS(Precise Event Based
Sampling) May Update Memory outside the BTS/PEBS Buffer
R75 X3 X3 Plan Fix
The Base of an LDT (Local Descriptor Table) Register May be
Non-zero on a Processor Supporting Intel® Extended Memory
64 Technology (Intel® EM64T)
R76 X3 Plan Fix
L-bit of the CS and LMA bit of the IA32_EFER Register May
Have an Erroneous Value For One Instruction Following a Mode
Transition in a Hyper-Threading Enabled Processor Supporting
Intel® Extended Memory 64 Technology (Intel® EM64T).
R77 X X X X X No Fix
Memory Ordering Failure May Occur with Snoop Filtering Third
Party Agents after Issuing and Completing a BWIL (Bus Write
Invalidate Line) or BLW (Bus Locked Write) Transaction
R78 X X X X X No Fix Control Register 2 (CR2) Can be Updated during a REP
MOVS/STOS Instruction with Fast Strings Enabled
R79 X X Plan Fix TPR (Task Priority Register) Updates during Voltage Transitions
of Power Management Events May Cause a System Hang
R80 X3 X3 No Fix REP STOS/MOVS Instructions with RCX >=2^32 May Cause a
System Hang
...

作者: Illuminati 时间: 2006-8-26 13:56
Intel 每个产品的每个 stepping 都会发布 Errata

拿这个来骗稿费也真是有点儿无知+无聊

作者: justinguo 时间: 2006-8-26 20:28

原帖由 珊瑚虫虫 于 2006-8-26 13:05 发表

哪130个？

http://www.amd.com/us-en/assets/ ... tech_docs/25759.pdf

自己看吧。N多。#51～#154。

作者: kingvieri 时间: 2006-8-26 23:48
革命尚未成功呀，努力

作者: 飞扬跋扈孙 时间: 2006-8-27 00:59
其实我们普通使用中不会知道有什么BUG的。。

作者: 神的马甲 时间: 2006-8-27 04:11
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作者: Illuminati 时间: 2006-8-27 12:32
有的确实是 bug，这个就是 Errata 列表，属于设计失误来的，但是绝大多数的 CPU 都有 50-200 个设计失误，但是基本可以通过升级 BIOS 或者给 OS 打补丁来解决

并非 1+1 算成 3 那种东西

作者: 肖镪濴 时间: 2006-8-27 12:53
问一下那个39号问题要在什么环境下才出现（就是引起系统崩溃的bug），本来想买了，现在又只有等了，如果那个环境我不可能用到，马上就去买。

作者: Illuminati 时间: 2006-8-27 12:55
哈哈，那你别买了，看 Errata 去买产品，真是全球头一个啊

作者: 肖镪濴 时间: 2006-8-27 13:00

原帖由 Illuminati 于 2006-8-27 12:55 发表
哈哈，那你别买了，看 Errata 去买产品，真是全球头一个啊

哦，照你的说法，intel根本没必要发布f步进的U了，你应该去Intel新闻部工作。
只不过想了解下intel发出警告的这个bug是何物，没想到遇到“神人”。

作者: Illuminati 时间: 2006-8-27 13:05
首先，这不是警告，这文章是给主板研发商看得，不是给最终用户看得

其次，你不是怕 Errata 里的东西会给你造成困扰么，那我就建议你别买了，你又不高兴

我最后再说一次，Errata 列表是给主板 BIOS 开发的人看得，一般用户看了发闲愁那就是杞人忧天。你用过这么多的电脑，哪一个因为 Errata 里的问题给你造成困扰了？别被无良小便忽悠了。要是这些话都被你曲解，对不起，自己愁去吧

作者: 我顶你的肺 时间: 2006-8-27 13:17
没米的人才会等！干脆等死算了！

作者: 肖镪濴 时间: 2006-8-27 16:05

原帖由 我顶你的肺 于 2006-8-27 13:17 发表
没米的人才会等！干脆等死算了！

好像你所谓的有米的人不会买6300。买6300的大多为了超频，这是米人的作风？今天去电脑城找了找没有米人才用的l625的6300心里着实有点不甘，觉得既然超不了多少还不如等F步进才有此一问。

作者: 林青豪 时间: 2006-8-27 16:08
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作者: 还在读童话 时间: 2006-8-27 20:00
强人，拜一下。:lol:

作者: FreeFox 时间: 2006-8-28 21:25
一般，这些缺陷都需要靠主板硬件设计、BIOS设计和操作系统设计人员来避免，极少数会需要应用程序设计人员进行特别设计来避免，当然有一种情况下没办法：就是你自己在编程序给自己用。

作者: BOSS 时间: 2006-8-28 21:41
bug ai65

作者: mm740 时间: 2006-8-29 13:35
郁闷刚发售就出新步进！

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