DAC与Jitter - POPPUR爱换 - Powered by Discuz!

Notes by Colin Miller: The rest of the industry calls this a Phase Lock Loop (assuming it is similar), operating with a healthy FIFO buffer to reclock the data, or simply reclock it completely without the PLL (a la Meridian) and attenuate if not eliminate jitter, but 'Jitter Jail' is a snazzier name. It may be that the Theta can alternate between these two methods, but it all boils down to a FIFO buffer on the input, and a new clock feeding information to the DAC process.8 D) `9 P0 R% P4 y/ U+ c {
" A/ d- g' v" k2 Z% `+ L1 S
Jitter is a timing error, an error in data rate, either over a very short time, or a very long time. Short periods of data rate error (too close together for a few samples, too far for a few more, etc.) are high-frequency jitter. Long periods of data rate error (too close for very many samples, gradually shifting to too far for many more, and so# E$ i A5 F9 C/ Q' J6 _3 B+ o! |
forth) are low frequency jitter. The only way to correct the error is to correct the timing. The only way to correct the timing is to space the data evenly at either a derived rate, or a known rate. The only way to do this is with some working room, which requires an input buffer, and then you can do what needs to be done, reclock it to the most uniform (evenly spaced) and preferably correct data rate.
( |5 W' t; Y1 T3 T9 i5 l; Q' q
+ G! E% b+ _. |& N9 ?& \7 c) `" u
In a perfect world, jitter would be no issue at all. In a next to perfect world, the DAC device would control the transport device's servo-controller that determines the data rate, and the only clock would be the master clock that times the DAC process, and so jitter would be very easily avoided with a small FIFO. That has yet to happen, to my knowledge.
2 r- Z3 E( s" w5 r, @
( y4 q' q \+ p/ I1 h& H# h( o
In a world almost as perfect as that, you have a FIFO buffer at the input, the DAC device figures out the rate by looking at the data, and reclocks the data completely independently of the incoming rate that would be carrying the jitter. In this scenario, the only jitter possible is that of the DAC's own clock itself, and any jitter prior to that is completely and utterly irrelevant, with one exception. If the error is of low frequency, i.e., goes too fast for awhile, then slows down for awhile, or as a most extreme example of the lowest frequency jitter, spits CD information out at 44,003 samples/second instead of 44,100 samples per second, you'll have buffer over- or underrun, in which case you either get dropouts, no sound, or a really nasty mess of a sound when the DAC tries to resynchronize with the rate. From the comment that your DVD player doesn't work with the "Jitter Jail," I'd guess that they're going this route for higher quality digital sources and that your DVD player is a particularly poor one. Stacey had this problem with his Meridian anti-jitter reclocking circuitry when he used a particular DVD player with the AC power, but it worked fine with the onboard battery power supply or when he used his Power Plant. He had to set his unit to operate in the more standard PLL with that source.
9 a$ {, ~- H5 h6 u8 Q9 @
7 x( _1 r. N8 Y x, u
The above illustrates why most of the industry resorts to a PLL, or Phase Lock Loop. This uses the same FIFO buffer, and attempts to smooth the data rate. It'd be like having a bunch of unruly school kids come in clumps through the gates at Disney Land, and the teacher assistant tries to get everyone evenly spaced before the turnstile and going through at a constant rate. He can't hold people up so that they're standing in the parking lot, nor can he get people to run to the parking lot, but if the average flow is steady, he can provide an even stream of screaming children. Every off-the-shelf DAC has a PLL, though some are better than others, and it's quite possible that Theta's is better than most. A better PLL requires a larger FIFO buffer, so to accommodate larger swings in the tide, so to speak, without having to compromise the new clock. For instance, if a CD was fed at 44,003 samples per second, a PLL would simply shift the master clock to 44,003 samples per second, not underrun the buffer, and still be able to attenuate the higher frequency jitter. This extreme example would result in a slight pitch shift, but where it gets really difficult is when it's shifting fast enough to cause modulation problems in the DAC, but slow enough to cause the FIFO buffer problems, an area where better jitter reduction schemes really shine.
! W) z5 |, [# ~* ?/ c
: n' \) z# x& P6 I# _8 p
This extreme example would result in a slight pitch shift, but where it gets really difficult is when it's shifting fast enough to cause modulation problems in the DAC, but slow enough to cause the FIFO buffer problems. Although the PLL circuit is the best way to attenuate jitter while managing the FIFO buffer with poor sources, the strength of the PLL's continuity is also its weakness in jitter reduction. In order to avoid buffer overflows or underflow with low frequency variations, the PLL will adjust the clock to match the data rate over a particular period, and if that jitter period is large enough (low in frequency) to make the PLL circuit adopt the change in data rate, the clock essentially tracks the jitter, passing the same timing errors on, even if slightly attenuated./ c/ E+ n) l7 J- o
S( I, j# {/ l9 v5 W3 N
It is here that we see that all PLL circuits are not created equal. A larger FIFO buffer, and possibly better buffer management in terms of how the clock adjusts to the amount of data in the buffer, mean that different PLL circuits have differing amounts of jitter attenuation, particularly in terms of low frequency jitter.* H4 H {- ]: L
7 v5 g; h3 s$ J
With better jitter reduction methods, the input buffer and the PLL can manage more low-frequency jitter while still attenuating the lower frequency jitter, whereas a poorer PLL circuit will simply begin to let the clock follow the lower frequency jitter, essentially passing it right onto the DAC. Since it is the lower frequency jitter that's the most audible, this is where the better jitter reduction schemes really shine. They still follow the rate of the incoming data, but their clocks remain more stable and jitter free in the presence of a less desirable source.
& t- `' V. L- R3 q+ ]

复制代码