Intel Readies New Memory Controller for Nehalem Chips
Intel Nehalem to Feature Triple-Channel Memory Controller
Intel’s code-named Nehalem processors have been discussed for nearly five years now, but Intel was tight-lipped enough in order not to disclose details of the new micro-architecture itself as well as implementation peculiarities. Nevertheless, recently Intel started to inform its partners about the future platforms, which means that at least some peculiarities of the new chips have come to light.
It is known that Nehalem as well as Westmere central processing units(CPUs) will use a new platform architecture and while the company does not directly state it, the new platform will hardly use processor system busses, but rather will feature point-to-point serial bus (which is currently referred to as Common Serial Bus or CSI) similar to Hyper-Transport or PCI Express. The new CPUs due in late 2008 will feature so-called dynamically scalable architecture, which means that Intel will be able to tailor its processor designs according to needs of various market segments.
In particular, Intel already announced that, among other things, it would be able to scale and configure caches, interconnect controllers as well as memory controllers. Already now Intel can reduce or increase cache sizes for various processors without many problems, whereas Advanced Micro Devices can enable or disable Hyper-Transport links within its processors depending on their positioning (e.g. AMD Opteron processors for multi-processor servers have three HT links, whereas Athlon 64 for1P machines have only one HT link). But Intel wants to go even further and scale the number of memory controller channels. According to PC Watch web-site, the top Nehalem processor code-named Bloomfield with four cores will have triple-channel DDR3 memory controller, whereas slightly less advanced may have less channels.Three memory channels supporting PC3-12800 (DDR3 1600MHz) memory would provide approximately 38.4GB/s memory bandwidth, up significantly from about 21.3GB/s memory bandwidth available today. Given that in 2009 Intel plans to release Nehalem processor with built-in graphics core,triple-channel memory controller may help to keep performance in 3D games on relatively high level.
Intel did not comment on the news-story.
AMD的首席销售和市场主管亨利理查德表示,AMD目前仍然领先Intel两年左右。
他表示“我们可以将自己的技术优势领先到2007/2008年
AMD新任制造生产副总裁Douglas Grose仍显得信心十足,
他说:“65nm已经过时了(old hat),AMD现在关注的是45nm。
原帖由 HeavenPR 于 2007-6-12 13:55 发表
3 通道! 居然被我猜中了!
既不记得我们当时说的 Nehalem,有人说是 3 核心的,现在看来好像不是 :lol:
我当时说会搭配 3 通道内存,Intel 居然听了我的话 w00t)
原帖由 flz821028 于 2007-6-14 17:03 发表
我也喜欢RAMBUS:loveliness:
不知道要等到何时,RAMBUS肯定希望重新回来的。但我觉得显卡不用RAMBUS的东西的话,内存更不会用的。
现在的DDR的延迟一代比一代…………
原帖由 Prescott 于 2007-6-12 12:15 发表
每个CPU的内存带宽是12.8G x 3 = 38.4GB/s :o
看以后谁还敢老是拿specfp_rate来说事。:whistling:
http://www.xbitlabs.com/news/cpu/display/20070610234912.html
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