L1 Cache
Each core in the Barcelona will have a dedicated 128KB, 2-way set associative L1 cache. This is twice the size of the L1 cache available to each core in the Intel Core 2 processor. The latency for the processor to retrieve data from the L1 cache is 3 clock cycles.
L2 Cache In the Core 2 design, Intel makes use of a large L2 cache shared between two cores. AMD, however, has chosen to use a smaller, dedicated 512KB L2 cache for each processing core. That means the quad-core Opteron processor will have four separate 512KB L2 caches. These caches are 16-way set associative, and the latency for each core to retrieve data from its L2 cache is 12 clock cycles.
L3 Cache The Barcelona features a large, shared L3 cache that is at least 2MB in size. This L3 cache will be shared by all cores, whether it's a dual-core or quad-core processor.
This cache is 32-way set associative and is based on a non-inclusive victim cache architecture. The latency for any core to retrieve data from the L3 cache is said to be less than 38 clock cycles. Oddly enough, AMD says the actual latency depends on the clock speed of the south bridge.作者: itany 时间: 2007-9-1 14:27
如果上边的数据是真的,那么K10低延迟和高延迟的差距并不足以产生大的影响,就像现在的AM2 65nm和90nm的差别。如果您说的是真的,产生的影响可能更大。但是我认为并不足以产生可以翻盘的影响。而且,缓存的延迟对于整数影响明显,对于密集型的浮点应用可能并不明显。作者: Prescott 时间: 2007-9-1 15:08