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标题: 继续YY CSI，现在叫QPI了，会不会有slot和cable？ [打印本页]

作者: itany 时间: 2007-9-25 19:58
标题: 继续YY CSI，现在叫QPI了，会不会有slot和cable？
Intel Quickpath Interconnect looms - even on slots and cables

Follows in the HTX paw prints

THIS WAS the first IDF where the upcoming Nehalem family and its QPI (Quickpath Interconnect, formerly known as CSI or Alpha EV7 v2) were described in more detail, with actual working systems doing their rounds at the show keynote podium. Of course, our friend David Kanter at realworldtech.com had an even more detailed overview on his site last month.

Now, as our readers know, QPI looks quite a bit like Hypertransport 3, which is no surprise since both draw roots from the Alpha EV7 interconnect in 2000 - if, at that time, Alpha continued instead of being stabbed for someone's personal interests from ongoing merger talks, things like FSB would have been a history long gone by now.

Going back to the common roots, we've given Hypertransport its due coverage on these pages over the past few years. That includes the HTX slot specification - bringing out the Hypertransport to the card slot and even external cable specification.

The idea is good - the HT3 peak bandwidth is comparable to the PCI-E v2 x16 slot bandwidth, but Hypertransport latency is easily one third, with remote memory access far easier to handle.

That means that any kind of remote virtual shared-memory cluster interconnects like Quadrics QsNet, or application specfic accelerators (whether FPGA or GPGPU) that need to access system memory quickly, would gain tremendously from sitting on a HTX slot instead of PCI-E. Couple of Opteron systems from IBM and HP even have those HTX slots on board, not to mention the Tyan and Iwill (now Flextronics) mainboards.

All these advantages apply to Quickpath as well - in fact, at up to 25.6 GByte/s per link, it is even faster than HT3, and has a very low overhead, low latency stack, with additional abilities like bifurcation (for instance, one half goes to I/O bridge, another to external cluster interconnect cable).

However, as far as I know, there was no slot or external cable spec done for the QPI yet - I did have a chat with the Intel folk in charge during the IDF, and response seems positive. After all, HTX already did clear the path.

The point is, Intel must do the slot standard marketing more aggressively than AMD or the Hypertransport Consortium did on HTX, with only a couple of cards coming out. The actual benefits are multiple: for instance, a (GP)GPU on a QPI slot could combine the usual large fast local card RAM with humongous but still reasonably quick-to-access system memory for anything from gigatextures to maths acceleration on large datasets which otherwise can't fit into card memory.

Yet, it is better than trying to expensively miniaturise everything in the CPU socket, for which Intel may also be less likely to share the info. The slot version costs would ultimately be pretty much the same as a similar high end PCIe v2 card, but with all the performance advantages mentioned.

Imagine the ability to attach multiple Larrabee or Terascale - or similar Nvidia or ATI gadgets running multiple acceleration jobs from 3D graphics to ray tracing to maths speedup to antivirus check directly in system memory from a QPI slot, yet not compromising their own on board features.

Or, just plug in a slot-to-cable converter and bring out a QPI cable to a QPI external switch, letting you attach, for instance, multiple four-socket Gainestown boxes into virtually unlimited NUMA-like systems. But, hold on, that will encroach on the Itanic cruiser turf? Who cares... Intel surely won't mind, we all know how "prominent" the "EPIC adventure storytelling" was at the recent IDF. µ

[ 本帖最后由 itany 于 2007-9-25 20:01 编辑 ]

作者: Prescott 时间: 2007-9-25 21:40
你一定又没有好好读RWT的文章了：

CSI is largely defined in a way that does not require a particular clocking mechanism for the physical layer. This is essential to balance current latency requirements, which tend to favor parallel interfaces, against future scalability, which requires truly serial technology. Clock encoding and clock and data recovery are prerequisites for optical interconnects, which will eventually be used to overcome the limitations of copper. By specifying CSI in an expansive fashion, the architects created a protocol stack that can naturally be extended from a parallel implementation over copper to optical communication.

[ 本帖最后由 Prescott 于 2007-9-25 21:43 编辑 ]

作者: siemens_wolf 时间: 2007-9-25 21:43
这个想法是一相情愿吧。。。。

作者: itany 时间: 2007-9-25 21:49

原帖由 Prescott 于 2007-9-25 21:40 发表
你一定又没有好好读RWT的文章了：

CSI is largely defined in a way that does not require a particular clocking mechanism for the physical layer. This is essential to balance current latency requi ...

您的意思是，在使用缆线连接的时候湖使用光纤进行并行传输，而不是使用铜线那样的串行么？

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