寻址空间对应表 | |||
处理器 | 虚拟内存寻址 | 物理内存寻址 | 物理内存容量 |
Prescott(P4,普通PC处理器) Nocona(Xeon,服务器处理器) | 48 bit | 36 bit | 64 GB |
EM64T的运行模式 | ||||
传统IA-32模式 | IA-32e扩展模式 | |||
保护模式 | 真实地址模式 | 真实8086模式 | 兼容模式 | 64位模式 |
64位模式 | 64兼容模式 | |||||
名称 | 数量 | 容量bits | 名称 | 数量 | 容量bits | |
通用寄存器(GPRs) | RAX,BX, RCX,RDX, RBP,RSI, RDI,RSP, R8-15 | 16 | 64 | EAX, EBX, ECX, EDX, EBP, ESI, EDI, ESP | 8 | 32 |
指令指针 | RIP | 1 | 64 | EIP | 1 | 32 |
浮点寄存器 | ST0-7 | 8 | 80 | ST0-7 | 8 | 80 |
多媒体寄存器 | MM0-7 | 8 | 64 | MM0-7 | 8 | 64 |
SSE寄存器 | XMM0-15 | 16 | 128 | XMM0-7 | 8 | 128 |
栈宽度 | 无 | 64 | 无 | 16或32 |
处理器型号 | 主频 | 核心 | L2 | 制程 | 前端总线FSB | 接口 |
Xeon | 2.80-3.60GHz | Nocona | 1M/2M | 90nm | 800 MHz | Socket604 |
Pentium 4 Extreme Edition | 3.73GHz | Prescott 2M | 2M | 90nm | 1066 MHz | LGA775 |
Pentium 4 660 | 3.6GHz | Prescott 2M | 90nm | 800MHz | LGA775 | |
Pentium 4 650 | 3.4GHz | Prescott 2M | 2M | 90nm | 800MHz | LGA775 |
Pentium 4 640 | 3.2GHz | Prescott 2M | 2M | 90nm | 800MHz | LGA775 |
Pentium 4 630 | 3.0GHz | Prescott 2M | 2M | 90nm | 800MHz | LGA775 |
- Full support for 64-bit integers: All general-purposeregisters (GPRs) are expanded from 32 bits to 64 bits, and allarithmetic and logical operations, memory-to-register andregister-to-memory operations, etc., are now directly supported for64-bit integers. Pushes and pops on the stack are always in eight-bytestrides, and pointers are eight bytes wide.
- Additional registers:In addition to increasing the size of the general-purpose registers,the number of named general-purpose registers is increased from eight(i.e. eax,ebx,ecx,edx,ebp,esp,esi,edi) in x86-32to 16. It is therefore possible to keep more local variables inregisters rather than on the stack, and to let registers holdfrequently accessed constants; arguments for small and fast subroutinesmay also be passed in registers to a greater extent. However, moreregisters also involves more saving and restoring of register contents,and AMD64 still has fewer registers than many common RISC processors (which typically have 32–64 registers) or VLIW-like machines such as the IA-64 (which has 128 registers).
- Additional XMM (SSE) registers: Similarly, the number of 128-bit XMM registers (used for Streaming SIMD instructions) is also increased from 8 to 16.
- Larger virtual address space: Current processor models implementing the AMD64 architecture can address up to 256 tebibytes of virtual address space (248 bytes). This limit can be raised in future implementations to 16 exbibytes (264 bytes). This is compared to just 4 gibibytesfor 32-bit x86. This means that very large files can be operated on bymapping the entire file into the process' address space (which isgenerally faster than working with file read/write calls), rather thanhaving to map regions of the file into and out of the address space.
- Larger physical address space: Current implementations of the AMD64 architecture can address up to 1 tebibyte of RAM (240 bytes); the architecture permits extending this to 4 pebibytes (252 bytes) in the future (limited by the page table entry format). In legacy mode, Physical Address Extension (PAE) is supported, as it is on most current 32-bit x86 processors, allowing access to a maximum of 64 gibibytes.
- Instruction pointer relative data access: Instructions can now reference data relative to the instruction pointer (RIP register). This makes position independent code, as is often used in shared libraries and code loaded at run time, more efficient.
- SSE instructions: The original AMD64 architecture adopted Intel's SSE and SSE2 as core instructions. SSE3 instructions were added in April 2005. SSE2 replaces the x87 instruction set's IEEE 80-bit precision,with the choice of either IEEE 32-bit or 64-bit floating-pointmathematics. This provides floating-point operations compatible withmany other modern CPUs. The SSE and SSE2 instructions have also beenextended to support the eight new XMM registers. SSE and SSE2 areavailable in 32-bit mode in modern x86 processors; however, if they'reused in 32-bit programs, those programs will only work on systems withprocessors that support them. This is not an issue in 64-bit programs,as all processors that support AMD64 support SSE and SSE2, so using SSEand SSE2 instructions instead of x87 instructions does not reduce theset of machines on which the programs will run. Since SSE and SSE2 aregenerally faster than, and duplicate most of the features of, thetraditional x87 instructions, MMX, and 3DNow!, the latter are redundant under AMD64.
- No-Execute bit:The “NX” bit (bit 63 of the page table entry) allows the operatingsystem to specify which pages of virtual address space can containexecutable code and which cannot. An attempt to execute code from apage tagged "no execute" will result in a memory access violation,similar to an attempt to write to a read-only page. This should make itmore difficult for malicious code to take control of the system via "buffer overrun" or "unchecked buffer" attacks. A similar feature has been available on x86 processors since the 80286as an attribute of segment descriptors; however, this works only on anentire segment at a time. Segmented addressing has long been consideredan obsolete mode of operation, and all current PC operating systems ineffect bypass it, setting all segments to a base address of 0 and asize of 4 GiB.AMD was the first x86-family vendor to support no-execute in linearaddressing mode. The feature is also available in legacy mode on AMD64processors, and recent Intel x86 processors, when PAE is used.
- Removal of older features: A number of "system programming"features of the x86 architecture are not used in modern operatingsystems and are not available on AMD64 in long (64-bit andcompatibility) mode. These include segmented addressing (although theFS and GS segments were retained in vestigial form for compatibilitywith Windows code)[3],the task state switch mechanism, and Virtual-8086 mode. These featuresdo of course remain fully implemented in "legacy mode," thus permittingthese processors to run 32-bit and 16-bit operating systems withoutmodification.
原帖由 动力音熊II 于 2007-11-21 04:24 发表
都是X-FI惹得祸啊。。。。
刚刚刻盘安装好了64位的Ubuntu,程序响应倒是蛮快的,eclipse也能够安装,32位的JDK确定是不行了,直接崩溃就是,没有去找64位的版本。。。flash有点小麻烦,没有去管它
直接奔到 ...
原帖由 acqwer 于 2007-11-21 09:17 发表
LZ去踩AMD和MS吧,这种中看不中用的技术就是AMD发布、MS推广的。
PS:现在的EMT64和X64毫无区别。
附:X86-64的说明
和EMT64对比一下,有什么区别?
原帖由 _MyST_Spring 于 2007-11-21 09:26 发表
楼主,其实Intel是很厚道的,它直接就告诉你了,现阶段所谓的64位技术的是64位扩展内存技术。而不是AMD忽悠你的所谓真正的64bit computing
原帖由 jaguard 于 2007-11-21 09:46 发表
这两者都是兼容x86指令集的64位微处理器架构,但EM64T与AMD64还是有一些不一样的地方,AMD64处理器中的NX位在Intel的处理器中将没有提供。
原帖由 acqwer 于 2007-11-21 09:17 发表
LZ去踩AMD和MS吧,这种中看不中用的技术就是AMD发布、MS推广的。
PS:现在的EMT64和X64毫无区别。
附:X86-64的说明
和EMT64对比一下,有什么区别?
原帖由 动力音熊II 于 2007-11-21 04:24 发表
都是X-FI惹得祸啊。。。。
刚刚刻盘安装好了64位的Ubuntu,程序响应倒是蛮快的,eclipse也能够安装,32位的JDK确定是不行了,直接崩溃就是,没有去找64位的版本。。。flash有点小麻烦,没有去管它
直接奔到 ...
原帖由 frankincense 于 2007-11-21 07:07 发表
很早以前就已经有PAE技术使32位CPU寻址大于4G的内存容量……
Windows Server的32位高端版本也支持大于4G的内存(Enterprise 8G,Datacenter 64G)
x86-64/Intal 64的出现倒是让微软不需要去考虑把服务器版的PAE技术 ...
文件名: XFiDrv_Linux_US-1.04.tar.gz | |
This download is a beta driver providing Linux® 64-bit OS support for Creative Sound Blaster® X-Fi™ series audio devices. For more details, read the rest of this web release note. Take note of the following:
|
原帖由 动力音熊II 于 2007-11-21 16:23 发表
看不惯这边有些家伙,天天的请注意称呼用词。,就像去年、前年这个时候拿着A64虐电热水壶P4的那群人一样
好像两个染布坊的两家小孩子对骂,都是一些言语讽刺的东西,没见多少有参考性的资料。
不是因为X-F ...
原帖由 来不及思考 于 2007-11-21 18:30 发表
你才是真正的装C
最烦你这种搞懂了一点点(其实全都是错的)就满世界拿来倾诉好像哥伦布发现新大陆红二军看到红六军阿Q碰见小尼姑生怕别人不知道你的“正确”观点一样
我问你,你转的这个破贴到底说的是什 ...
原帖由 动力音熊II 于 2007-11-21 16:06 发表
。。。。64位的Linux是要流畅很多啊,难道是新装系统的错觉?再用几天看看。。。没打算这么早用64位的WIN,只是找一个稳定的环境做事而已,比较反感现在VISTA一直读硬盘
硬盘灯常亮的时候,什么事都做不了。。: ...
原帖由 动力音熊II 于 2007-11-21 19:51 发表
发在GZ的最后一帖,反正这边好玩的人都走光了。。。。
各位,你们慢慢YY吧。GZ不是以前那个好玩的地方了,没有什么技术贴可看、也没有多少娱乐贴可以水,水区也挂了,没意思。可能是我不适合这边玩,嗯嗯。。。。 ...
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