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标题: 求原文：关于Nehalem的QPI和时钟问题 [打印本页]

作者: itany 时间: 2008-6-17 21:14
标题: 求原文：关于Nehalem的QPI和时钟问题

Intel谈Nehalem带宽、扩展性、频率

驱动之家[原创] 作者：上方文Q 编辑：上方文Q　2008-06-17 17:20:00 2686 人阅读 [投递]

在夏威夷召开的超大规模集成电路技术研讨会上，来自Intel的Rajesh Kumar透露了一些有关Nehalem处理器的消息。

Kumar首先给出了一些带宽数字：Nehalem处理器间带宽可达25GB/s，内存带宽则能达到32GB/s，“都是(Intel)当今最好产品的大约3倍”。为了达到这种高带宽，Intel引入了一种名为“低抖动时钟”的技术，可以“在部分情况下将频率的不稳定性减少一个数量级”。

Kumar还谈到了Intel是如何将Nehalem架构跨平台部署到桌面、笔记本和服务器上的。他说，Nehalem的所有内部模块，包括处理核心、内存控制器、I/O界面，都运行在非耦合(decoupled)状态下，因此Intel可以独立地调节它们的频率和电压。这当然不是Intel的首创，不过Intel的新意是在各种模块之间使用了一种同步界面。异步界面会带来更高的延迟和不稳定性，“测试五套不同的系统就会得到五个不同的结果”，而有了同步界面，Nehalem的内存缓存延迟要比现有产品小得多。

最后Kumar还提到了Nehalem的自适应频率发生系统。基本上，Nehalem会根据实际功耗在每个循环内调整自己的频率，结果就是可以在特定电压提高频率，或者在特定频率下降低电压。不过，Nehalem没过几个循环就会对不同的时钟频率取平均值，因此从外边看，“任何时候的频率都是固定的”。

作者: itany 时间: 2008-6-17 21:14
怎么好东西到了Mydrivers，都变成莫名其妙的呢？

作者: wjuncn 时间: 2008-6-17 23:51
看的不太懂，，，帮你往上顶顶。。

作者: 百事可乐 时间: 2008-6-18 02:14
不小心搜到了

Intel gives peek into Nehalem bag of tricks
by Cyril Kowaliski — 11:23 PM on June 16, 2008

In a phone conference this morning, Intel gave a little preview of the papers it plans to unveil at the VLSI Symposia on Technology and Circuits this week in Hawaii. Much of the discussion focused on hairy electrical engineering specifics, but one of the speakers revealed a few interesting details about what Intel has in store for its next-generation Nehalem processor architecture.

Intel Fellow Rajesh Kumar opened his expose by throwing around some bandwidth numbers. Nehalem can hit 25GB/s of socket-to-socket bandwidth and a staggering 32GB/s of main memory bandwidth—figures Kumar said are both "about 3X larger than [Intel's] best competition today." To achieve such prodigal bandwidth, Intel implemented a technique called low-jitter clocking, which can "reduce uncertainty in clocks by, in some cases, an order of magnitude compared to what was achieved before."

Kumar also went into a little bit of detail about how Intel designed Nehalem to scale across mobile, desktop, and server segments. The processor runs all of its internal components—the CPU cores, memory controller, and I/O—in a decoupled fashion, so one can tune their respective frequencies and voltages independently. This isn't a new idea, Kumar stressed, but Intel's implementation is new in that it uses a synchronous interface between those components. Most past implementations have asynchronous interfaces, he claimed, which result in both higher latency and indeterminism—"if you test five different systems, you will get five different results." Because of the synchronous approach, Nehalem's memory-to-cache latency is allegedly "drastically smaller" than that of the competition.

Last, but not least, Kumar briefly described Nehalem's adaptive frequency clocking system. If I understood this part correctly, the processor basically adapts its frequency every cycle based on power draw. As a result, Kumar said Nehalem can hit a higher frequency at a given voltage or hit a lower voltage at a given frequency compared to existing chips. However, the CPU also averages the effects of clock speed variations after every few cycles, so from an outside perspective, "you are getting a fixed frequency all the time."

Nehalem remains on track for a launch in the fourth quarter of this year.

作者: itany 时间: 2008-6-18 09:11
多谢……
个人觉得Intel还是把RAMBUS收了比较好。

作者: hyj201 时间: 2008-6-18 10:06
都运行在非耦合(decoupled)状态下

我不太明有米高人解释一下？

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