Sunil R. Shenoy Vice President, Intel Architecture Group
General Manager, Visual and Parallel Computing Group
INTEL CORPORATION Sunil R. Shenoy is vice president of the Intel Architecture Group (IAG) and general manager of the Visual and Parallel Computing Group (VPG) for Intel Corporation. He is responsible for definition and development of visual computing for Intel's microprocessors and for highly parallel microprocessor development for servers and workstations.
Shenoy lives in Oregon and oversees development teams located throughout the United States, India and other geographies.
Since joining the company in 1981, Shenoy has held technical and management positions related to microprocessor design and development. Shenoy spearheaded the design and delivery of multiple generations of the Intel® Pentium® 4 processors and oversaw the development of the recently announced "Nehalem" generation of microprocessors.
Shenoy has received two Intel Achievement Awards and holds 16 patents in microprocessor design methods and apparatus.
Shenoy earned an MBA from the University of Oregon in 1995. He also received his master's and bachelor's degrees in electrical engineering from Syracuse University in 1981 and the Indian Institute of Technology in Mumbai in 1980, respectively.
“Hswell的缓存架构和参赛概略:L1-D仍然为32K-8way-4Cycle、L1-I提升为64K-8way-3Cycle;L2提升为512K-8way-9Cycle、L3每核心平均3M,无论任何阶层都是24Way—25Cycle,且采用256Bit Ring Bus片内环形总线进行连接!”
我觉得这段很不可思议,相比想在SNB不是进步了,是退步了。L2的速度足足慢了近30%,L3也慢了10%左右,L3 3MB/Core也偏小(只讨论不删减版)。故我个人认为楼主说的不足信。
“Hswell的缓存架构和参赛概略:L1-D仍然为32K-8way-4Cycle、L1-I提升为64K-8way-3Cycle;L2提升为512K-8way-9Cycle、L3每核心平均3M,无论任何阶层都是24Way—25Cycle,且采用256Bit Ring Bus片内环形总线进行连接!”
我觉得这段很不可思议,相比现在SNB不是进步了,是退步了。L2的速度足足慢了近30%,L3也慢了10%左右,L3 3MB/Core也偏小(只讨论不删减版)。故我个人认为楼主说的不足信。