|
想换个Opteron 165+ J( t6 `! u" [% P; |
自己用的板子是微星 K8N Neo4 Platinum白金板
, s! R B7 S+ W4 h: JSOCKET 939 K8 的2 A3 o, i2 _5 S" x6 c; t# V" U
到底算可以用不?; }; K' V% Y* o: L+ J
去微星网站上看了下CPU支持列表如下:
( T! E4 k6 {: D
" l7 `$ t0 m- X% P/ p7 T4 _* O% u3 D# ^! Y
CPU FSB 倍頻 測試結果
8 E9 z6 y5 w0 I0 P; }0 [. y: e7 i* }Athlon 64 (ClawHammer, 130nm, L2 Cache 512KB)
0 A7 B5 g. _3 S. K5 P; I) ^% eAthlon 64 3500+ (CG version) 200 11 OK 9 _' v5 u6 t2 `7 p i3 o
Athlon 64 (ClawHammer, 130nm, L2 Cache 1MB)
& L$ e( ^, ^5 mAthlon 64 4000+ (CG version) 200 12 OK " F$ R* d/ {4 U$ a# e6 L" a9 @( `3 A1 Y
Athlon 64 (Newcastle, 130nm, L2 Cache 512KB) 9 E8 j1 X$ v1 O( x* |6 F& y0 @
Athlon 64 3000+ (CG version) 200 9 OK % O# |6 w3 Z) o
Athlon 64 3200+ (CG version) 200 10 OK - P+ k4 A) o7 C. z7 x3 \& ]1 N& i% f
Athlon 64 3400+ (CG version, Hypertransport) 200 11 OK
% ? j2 Y0 n% R( c; X# lAthlon 64 3500+ (CG version) 200 11 OK
# e( |0 t; j! c1 iAthlon 64 3800+ (CG version) 200 12 OK
( `7 |! I7 a, [+ CAthlon 64 (Winchester, 90nm, L2 Cache 512KB)
) m4 x0 W9 _! e Q; w0 u" f9 hAthlon 64 3000+ (D0 version) 200 9 OK
# e% _- Q# y, RAthlon 64 3200+ (D0 version) 200 10 OK
+ m3 N1 V C7 x. ~$ b6 uAthlon 64 3500+ (D0 version) 200 11 OK ; G' j! X+ Q& W
Athlon 64 (Venice, 90nm, L2 Cache 512KB)
+ }/ c6 }& H& Y0 d8 |1 f4 sAthlon 64 3000+ (E3 version) 200 9 OK
9 [) H2 W& U- j, xAthlon 64 3200+ (E3 version) 200 10 OK
& d- T' P; J. E3 w# N7 j5 N0 xAthlon 64 3500+ (E3 version) 200 11 OK
0 ~0 g' s: [/ }/ S" L+ P) @% dAthlon 64 3800+ (E3 version) 200 12 OK 5 ~, j3 S, r' t
Athlon 64 (Venice, 90nm, L2 Cache 512KB) # K7 l4 Z6 l1 k$ Q$ Y
Athlon 64 3000+ (E6 version) 200 9 OK * F4 }1 ]6 u) \
Athlon 64 3200+ (E6 version) 200 10 OK
0 n3 W, O5 ]5 [7 X T* P# {/ ?Athlon 64 3400+ (E6 version) 200 11 OK ) \; L! K: y1 K9 |) t3 }2 \
Athlon 64 3500+ (E6 version) 200 11 OK
, l/ M2 U, {. H* c: U, g5 K! p& TAthlon 64 3800+ (E6 version) 200 12 OK % z) C3 }6 W( ?& ~/ P
Athlon 64 (San Diego, 90nm, L2 Cache 1MB)
- Z5 w4 W9 V3 r) H# Q# t3 ]3 tAthlon 64 3700+ (E4 version) 200 11 OK
2 M8 c6 T) j. }7 x# H- V$ i; rAthlon 64 4000+ (E4 version) 200 12 OK ) [( h6 t M' v, \3 Q
Athlon 64 FX (ClawHammer, 130nm, L2 Cache 1MB) - P: y8 d- s+ t; n
Athlon 64 FX53 (CG version) 200 12 OK
8 w5 A; |! J# Y# L! q DAthlon 64 FX55 (CG version) 200 13 OK 3 x; H1 S7 t1 f* j5 c
Athlon 64 FX (San Diego, 90nm, L2 Cache 1MB) 1 C x7 {, e u
Athlon 64 FX-55 (E4 version) 200 13 OK
! B: s% M2 p1 @0 P) f7 D9 QAthlon 64 FX-57 (E4 version) 200 14 OK
@* q1 a$ q/ e3 ]/ z1 QAthlon 64 X2 Dual-Core (Manchester, 90nm, L2 Cache 2 x 512KB)
5 L$ H* ~+ @* r: b5 w0 g4 ]Athlon 64 X2 Dual-Core 3800+ (E4 version) 200 10 OK
0 ~* t4 ]0 O" Z1 tAthlon 64 X2 Dual-Core 4200+ (E4 version) 200 11 OK % V7 I+ g) J0 l, s
Athlon 64 X2 Dual-Core 4600+ (E4 version) 200 12 OK
& N- B: Q: }4 l; M- gAthlon 64 X2 Dual-Core (Manchester, 90nm, L2 Cache 2 x 512KB) " I- K# `- ~! r0 r
Athlon 64 X2 Dual-Core 3800+ (E6 version) 200 10 OK
4 ]. g' I9 g" d* I4 |5 s! cAthlon 64 X2 Dual-Core 4200+ (E6 version) 200 11 OK 4 U/ `# D* |& U0 e0 r9 Y/ Z* K
Athlon 64 X2 Dual-Core 4600+ (E6 version) 200 12 OK 4 T( ^0 }/ C6 n! }
Athlon 64 X2 Dual-Core (Toledo, 90nm, L2 Cache 2 x 1MB) ' V1 a+ K% h- b5 }% u8 n
Athlon 64 X2 Dual-Core 4400+ (E6 version) 200 11 OK
# R2 S/ f; P% N4 W" i5 PAthlon 64 X2 Dual-Core 4800+ (E6 version) 200 12 OK |
|