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http://we.pcinlife.com/thread-663389-1-1.html
IBM
Design of the POWER6™ Microprocessor
The POWER6™ microprocessor combines ultra-high frequency operation, aggressive
power reduction, a highly scalable memory subsystem, and mainframe-like reliability,
availability, and serviceability. The 341mm2 700M transistor dual-core microprocessor
is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It
operates at clock frequencies over 5GHz in high-performance applications, and
consumes under 100W in power-sensitive applications.
A Distributed Critical-Path Timing Monitor for a 65nm High-Performance
Microprocessor
A distributed critical-path timing monitor (CPM) is designed as part of the POWER6TM
microprocessor in 65nm SOI. The CPM is capable of monitoring timing margin, process
variation, localized noise and VDD droop, or clock stability. It tracks critical-path delay to
within 3 FO2 delays at extreme operating voltages with a standard deviation less than
1/2 an FO2 delay. The CPM detects DC VDD droops greater than 10mV and tracks timing
changes greater than 1 FO2 delay. |
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