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EVG 公布业界第一个直径 450mm SOI 晶圆的 Wafer Bonding 系统

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1#
发表于 2011-7-14 19:45 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
EVG Unveils Industry’s First Wafer Bonding System for 450mm SOI Wafers.



Soitec Set to Make 450mm SOI Wafers
[07/13/2011 10:51 PM]
by Anton Shilov

EV Group (EVG), a leading supplier of wafer bonding and lithography equipment has unveiled the semiconductor industry's first bonding system for 450mm-diameter wafers manufactured from silicon-on-insulator (SOI) substrates. The new machines will allow making 450mm SOI wafers that will then used to make chips. The main intrigue is which company will use such wafers first.

The new wafer bonding system - dubbed the EVG850SOI/450 mm - was created to support and facilitate the industry transition to 450mm wafers from the current 300mm standard. The new EVG850SOI/450-mm wafer bonding system is a fully automated tool for production-level fabrication of SOI wafers. Since chipmakers will need an interim solution to optimize productivity for existing 300mm capacity as the migration to 450mm proceeds over the next few years, the system can serve as a bridge tool, allowing processing of both wafer sizes.

Wafer bonding is a crucial technique for fabricating SOI wafers, as it enables achievement of high-quality, single-crystal silicon films on one insulating layer to form SOI substrates

The EVG850SOI/450 mm consists of two process modules: a cleaning module for cleaning and pre-conditioning of wafers before wafer bonding, and an SOI pre-bonding module. In the pre-bonding module, the two silicon wafers are joined together either in a vacuum or in an atmospheric chamber. The tool is equipped with state-of-the-art 450mm load ports and front opening unified pods (FOUPs). Most of the particle and metal ion contamination tests will be performed on 300-mm wafers due to the lack of 450mm metrology systems.  The first tool in EVG's 450mm arsenal, the new bonder will serve as the key starting point for the production of 450mm SOI wafers, and can be utilized for the development of other EV Group 450mm products, such as mask aligners and coating systems. An extension of the system with additional modules is planned as a further step to increase wafer throughput.

Leading SOI wafer provider Soitec will install, test and qualify the first EVG850SOI/450mm system at its Grenoble, France, headquarters. Delivery is slated for fall 2011. Unfortunately, it is completely unclear which of the semiconductor manufacturers will actually use such substrates.

At present, the leading semiconductor companies to use silicon-on-insulator wafers are Globalfoundries, IBM and Samsung Semiconductor. Neither Globalfoundries nor IBM have announced plans to migrate to 450mm wafers. Still, there are rumours that Globalfoundries is building new modules of its Fab 8 so that they were 450mm ready. Samsung Electronics has announced collaboration with Intel Corp. and Taiwan Semiconductor Manufacturing Company over standardization of 450mm equipment. But neither Intel nor TSMC plan to use SOI. At this point it is likely that Samsung will be the first to test the 450mm wafers.

"One of the most important SOI fabrication processes based on wafer bonding is the Smart Cut layer transfer technology from Soitec, with whom EV Group has a longstanding collaborative relationship. Soitec is the ideal recipient of the first EVG 450mm SOI wafer bonding system, and their evaluation of the alpha-tool will be invaluable for optimizing the system modules,” said Paul Lindner, executive technology director of EV Group.

According to EVG, SOI is expected to play an enabling role in the shift to 450 mm, as it not only answers most of the scaling challenges, but it also delivers better power/performance for sub-22nm CMOS and 3D technologies compared to similar-geometry bulk CMOS.

"Soitec is willing to position in the 450-mm transition. With the launch of this new system, EV Group is offering the semiconductor industry a highly viable solution to ease the transition to 450mm wafers. With our well established SOI material playing an increasingly greater role in fabricating next-generation ICs, we look forward to working with EVG to ensure this new system is ready to enter mainstream production in a timely fashion,” said Paul Boudre, chief operating officer of Soitec.
2#
发表于 2011-7-14 20:15 | 只看该作者
要好好学英文
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westlee 该用户已被删除
3#
发表于 2011-7-14 20:16 | 只看该作者
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4#
发表于 2011-7-14 23:29 | 只看该作者
TSMC的FAB15压根不支持也没可能支持450mm,鬼知道他的18寸啥时候能推起来……
18寸的推进速度是极度缓慢和痛苦的,现在只有INTEL的D1X5声称支持。大晶圆看着挺香,实际上一算时间成本最后的收益根本没提升多少。
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头像被屏蔽
5#
发表于 2011-7-15 09:18 | 只看该作者
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6#
 楼主| 发表于 2011-7-15 09:32 | 只看该作者
Intel 当初的计划是 2014 年量产 450mm wafer。
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potomac 该用户已被删除
7#
发表于 2011-7-15 22:06 | 只看该作者
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8#
发表于 2011-7-15 23:33 | 只看该作者
potomac 发表于 2011-7-15 22:06
大饼一旦投产可能意味着会堆叠封装DRAM进去。
不然主流设计还真难消化掉这样大的面积。

TSV和18寸其实没啥联系。
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potomac 该用户已被删除
9#
发表于 2011-7-15 23:46 | 只看该作者
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10#
发表于 2011-7-15 23:50 | 只看该作者
potomac 发表于 2011-7-15 23:46
技术上是没啥关系。但多出来的产能(面积)怎么解决呢?
能和CPU产能配套的做法,可能只有生产RAM了。{l ...

我不说了么,一时间成本来考量,其实18寸并没好多少的。
表面上看面积大了,但实际上单位时间的产能,并没有你想象中的那样猛增。

如果以TSMC的现状来形容的话,如果FAB11~15全换上18寸,多出来的产能还是填不平所有需求,那帮家伙还是要为包场而打架的。
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potomac 该用户已被删除
11#
发表于 2011-7-16 00:23 | 只看该作者
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12#
发表于 2011-7-16 00:27 | 只看该作者
本帖最后由 mooncocoon 于 2011-7-16 00:30 编辑

面积翻倍,处理方式跟着也就复杂了,工序也多了,时间是一把杀猪刀。
现在已有的报告普遍指向不考虑良率,算上时间成本之后产能只能提升110%~120%,相当对不起225%的面积提升。

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13#
发表于 2011-7-16 08:38 | 只看该作者
多出来的产能可以用来生产高性能的显存啊~不要给三星一家垄断高端显存市场了{victory:]
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potomac 该用户已被删除
14#
发表于 2011-7-16 14:32 | 只看该作者
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15#
发表于 2011-7-16 19:00 | 只看该作者
G81 发表于 2011-7-16 08:38
多出来的产能可以用来生产高性能的显存啊~不要给三星一家垄断高端显存市场了

18寸晶圆厂造的内存是奢侈品吧
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16#
发表于 2011-8-27 13:29 | 只看该作者
inmark 发表于 2011-7-16 19:00
18寸晶圆厂造的内存是奢侈品吧

高端显卡消费得起啊{titter:]
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