Intel talks optimization (Core 2)

Edison

Intel talks optimization
Intel's Tokyo presentation included a general overview of optimization for Core 2. I've got the PowerPoint slides from that, and here's an Intel-supplied picture of the Core 2 microarchitecture:


Intel's Core 2 Microarchitecture
If you've seen the above diagram before, then you'll notice that there's a new number in there. From what I know, the Tokyo presentation is the first time that Intel has disclosed this much information about Core 2's fetch and predecode phases:

18-deep instruction queue
6 instructions can be written per cycle (by PreDecode)
5 instructions can be read per cycle
Implements a single "Macro-fusion" per cycle
Delivers complete instructions to the Decode stage

http://arstechnica.com/news.ars/post/20060626-7135.html

雨之间

show me the performance after optimization

hopetoknow2

原帖由 Edison 于 2006-6-27 12:26 发表
Intel talks optimization
Intel's Tokyo presentation included a general overview of optimization for Core 2. I've got the PowerPoint slides from that, and here's an Intel-supplied picture of the Co ...

这预示:
预译码的输出带宽是6指令
指令队列长度为18指令
在指令队列中， 就要实现宏指令融合了

[ 本帖最后由 hopetoknow2 于 2006-6-27 16:03 编辑 ]