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INQ: Power 6Ê×·¢ÆµÂÊ2.8GHzµ½3.2GHz

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http://www.theinquirer.net/default.aspx?article=38570

Childe Rolande IBM very late on road to AIX 5.4

So delaying Power 6 in its cut down speeds

By Mike Magee in Bangalore: ÐÇÆÚËÄ 29 ÈýÔÂ 2007, 03:01
SOURCES HERE told your outsauced editor that IBM's AIX 5.4 version is severely delayed making things tough for Big Blue's launch of the Power 6.

There will be a whole lot of reverse engineering going on in the furious ride to AIX 5.4. It also appears, we heard through the gripevine, that Big Blue is contemplating introducing Mr Power 6 at lower clock rates than first anticipated. We're now expecting intros at the 2.8GHz to 3.2GHz level seeing as IBM is hoping its ROCK will be far from being in a hard place.

Meanwhile, Mr AIX 5.4, when he finishes his furious gallop from the outsourcers at Ghent will likely have an AIX-to-AIX layer which won't mind schmoozing with Solaris Containers.

* DID YOU know that part of the phenomenal success of Indian's AirTel is because practically every single nut, bolt and screw of the infrastructure is managed by Big Blue?
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2#
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3#
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4#
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5#
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http://we.pcinlife.com/thread-663389-1-1.html

IBM

Design of the POWER6™ Microprocessor

The POWER6™ microprocessor combines ultra-high frequency operation, aggressive
power reduction, a highly scalable memory subsystem, and mainframe-like reliability,
availability, and serviceability. The 341mm2 700M transistor dual-core microprocessor
is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It
operates at clock frequencies over 5GHz in high-performance applications
, and
consumes under 100W in power-sensitive applications.

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance
Microprocessor

A distributed critical-path timing monitor (CPM) is designed as part of the POWER6TM
microprocessor in 65nm SOI. The CPM is capable of monitoring timing margin, process
variation, localized noise and VDD droop, or clock stability. It tracks critical-path delay to
within 3 FO2 delays at extreme operating voltages with a standard deviation less than
1/2 an FO2 delay. The CPM detects DC VDD droops greater than 10mV and tracks timing
changes greater than 1 FO2 delay.
7#
 Â¥Ö÷| ·¢±íÓÚ 2007-3-29 18:04 | Ö»¿´¸Ã×÷Õß
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http://we.pcinlife.com/viewthrea ... Ö=11807#pid12768827

[ ±¾Ìû×îºóÓÉ Prescott ÓÚ 2007-3-29 18:05 ±à¼­ ]
8#
·¢±íÓÚ 2007-3-29 18:05 | Ö»¿´¸Ã×÷Õß
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9#
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11#
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12#
·¢±íÓÚ 2007-3-29 18:29 | Ö»¿´¸Ã×÷Õß
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13#
·¢±íÓÚ 2007-3-29 18:32 | Ö»¿´¸Ã×÷Õß
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14#
·¢±íÓÚ 2007-3-29 19:13 | Ö»¿´¸Ã×÷Õß
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