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http://www.techarp.com/showarticle.aspx?artno=424&pgno=2
L1 Cache
Each core in the Barcelona will have a dedicated 128KB, 2-way set associative L1 cache. This is twice the size of the L1 cache available to each core in the Intel Core 2 processor. The latency for the processor to retrieve data from the L1 cache is 3 clock cycles.
L2 Cache
In the Core 2 design, Intel makes use of a large L2 cache shared between two cores. AMD, however, has chosen to use a smaller, dedicated 512KB L2 cache for each processing core. That means the quad-core Opteron processor will have four separate 512KB L2 caches. These caches are 16-way set associative, and the latency for each core to retrieve data from its L2 cache is 12 clock cycles.
L3 Cache
The Barcelona features a large, shared L3 cache that is at least 2MB in size. This L3 cache will be shared by all cores, whether it's a dual-core or quad-core processor.
This cache is 32-way set associative and is based on a non-inclusive victim cache architecture. The latency for any core to retrieve data from the L3 cache is said to be less than 38 clock cycles. Oddly enough, AMD says the actual latency depends on the clock speed of the south bridge. |
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