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5.4 An Integrated Quad-Core Opteron™ Processor
J. Dorsey1
, S. Searles1
, M. Ciraula1
, S. Johnson1
, N. Bujanos1
, D. Wu1
,
M. Braganza1
, S. Meyers1
, E. Fang2
, R. Kumar
2
1
AMD, Austin, TX
2
AMD, Sunnyvale, CAAcknowledgements:
The authors gratefully acknowledge the global AMD team that made this
design a reality.
References:
[1] J. Warnock, D. Wendel, T. Aipperspach, et al., “Circuit Design
Techniques for a First-Generation Cell Broadband Engine Processor,”
IEEE J. Solid State Circuits, vol. 41, pp. 1692-1706, Aug., 2006.
[2] HyperTransport I/O Link Specification Revision 3.00, HyperTransport
Consortium, http://www.hypertransport.org/tech/tech_specs.cfm. |
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