|
|
10GBASE-T的物理层编码很复杂，IEEE标准中的描述也很晦涩，这里给大家简单介绍一下相关的原理：
10GBASE-T有4条数据通道, 每条为800M symbol/s的符号率, 而每个symbol有16级, 相当于4bit. 这样计算出来10GBASE-T物理层带宽就应该是4*800*4=12800Mbit/s.
(不知为何google上查不到这个物理层带宽值).
在发送数据时, 50个64bit数据编组(3200bit), 先采用64b/65b编码再加上1个字节CRC校验再加上1个额外的bit, 变成50*65+8+1=3259bit, 然后3259bit中的3*512bit直接传输, 剩下1723bit加上325bit的LDPC校验位, 总共是2048+1576=3624bits. 再经过一些编码, 最后组合成512个DSQ128 symbol(也就是1024个PAM16 symbol)发送.
这样总体的效果就是用1024个symbol发送了3200bit数据, 也就是说每个symbol发送的有效数据为3200/1024=3.125bit. 从而可以计算出数据层看到的带宽正好是4*800*3.125=10000Mbit/s.
以上描述不一定很准确，如有问题欢迎指正。
附IEEE 802.3an-2006中的相关描述:
The 10GBASE-T PHY employs full duplex baseband transmission over four pairs of balanced cabling. The aggregate data rate of 10 Gb/s is achieved by transmitting 2500 Mb/s in each direction simultaneously on each wire pair, as shown in Figure 55–2. Baseband 16-level PAM signaling with a modulation rate of 800 Megasymbol per second is used on each of the wire pairs. Ethernet data and control characters are encoded at a rate of 3.125 information bits per PAM16 symbol, along with auxiliary channel bits. Two consecutively transmitted PAM16 symbols are considered as one two-dimensional (2D) symbol. The 2D symbols are selected from a constrained constellation of 128 maximally spaced 2D symbols, called DSQ1287 (double square 128). After link startup, PHY frames consisting of 512 DSQ128 symbols are continuously transmitted. The DSQ128 symbols are determined by 7-bit labels, each comprising 3 uncoded bits and 4 LDPC-encoded bits. The 512 DSQ128 symbols of one PHY frame are transmitted as 4 × 256 PAM16 symbols over the four wire pairs. Data and Control symbols are embedded in a framing scheme that runs continuously after startup of the link. The modulation symbol rate of 800 Msymbols/s results in a symbol period of 1.25 ns.
The DSQ128 symbols are obtained by concatenating two time-adjacent 1D PAM16 symbols and retaining among the 256 possible Cartesian product combinations, 128 maximally spaced 2D symbols. The resulting checkerboard constellation is based on a lattice called RZ2 in the literature (see Forney [B28A]). DSQ constellations have previously been introduced under the name “AMPM” (see [B28C] for examples of 8 point and 32 point AMPM/DSQ constellations).
In the transmit direction, in normal mode, the PCS receives eight XGMII data octets provided by two consecutive transfers on the XGMII service interface on TXD<31:0> and groups them into 64-bit blocks with the 64-bit block boundaries aligned with the boundary of the two XGMII transfers. Each group of eight octets along with the data/control indications is transcoded into a 65-bit block. The resulting 65-bit blocks are scrambled and assembled in a group of 50 blocks. Adding CRC8 check bits yields a CRC-checked Ethernet payload of 50 × 65 + 8 = 3258 bits. An auxiliary channel bit is added to obtain a block of 3259 bits.
The 3259 bits are divided into 3 × 512 bits and 1723 bits. The 3 × 512 bits, among them the auxiliary channel bit, remain uncoded. The 1723 bits are encoded by a systematic LDPC(1723,2048) encoder, which adds 325 LDPC check bits to form an LDPC codeword of 2048 coded bits. The 3 × 512 uncoded bits and the 2048 = 4 × 512 coded bits are arranged in a frame of 512 7-bit labels. Each 7-bit label comprises 3 uncoded bits and 4 coded bits.
The 512 7-bit labels are mapped into 512 2D modulation symbols selected from a DSQ128 constellation. The DSQ128 symbols are obtained by concatenating two time-adjacent 1D PAM16 symbols and retaining
among the 256 possible Cartesian product combinations, 128 maximally spaced 2D symbols. The resulting checkerboard constellation is based on a lattice called RZ2 in the literature (see Forney [B28A]). The DSQ128 constellation is partitioned into 16 subsets, each subset containing 8 maximally spaced 2D symbols. The 4 coded bits of each 7-bit label select one DSQ128 subset, and the 3 uncoded bits of the label select one 2D symbol in this subset.
The obtained PHY frame of 512 DSQ128 symbols is passed on to the PMA as PMA_UNITDATA.request. The PMA transmits the DSQ128 symbols over the four wire pairs in the form of 256 constituent PAM16
symbols per pair. Details of the PCS function are covered in 55.3. In the receive direction, in normal mode, the PCS processes code-groups received from the remote PHY via the PMA in 256 4D symbol blocks and maps them to the XGMII service interface in the receive path. In this receive processing scheme, symbol clock synchronization is done by the PMA Receive function. The PCS functions and state diagrams are specified in 55.3. The signals provided by the PCS at the XGMII conform to the interface requirements of Clause 46. The interface to the PMA is an abstract message-passing interface specified in 55.2.
|
|
IP卡
狗仔卡
楼主
显身卡
发表于 2011-12-5 22:12