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9260-8i uart得到的信息,求有弄过的指点!

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发表于 2014-5-7 01:03 | 显示全部楼层 |阅读模式


通过COM口得到一些启动过程,其中有多处有
Press '!' within 3 seconds to enter debugger before INIT
但是按了!也没用,或者是有其它的方法进入,希望有调试过的朋友指点指点

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 楼主| 发表于 2014-5-7 01:09 | 显示全部楼层
本次启动完整过程,中间没做任何操作,不过与前几次想比,有些是重复的,不知何故,看过TTYlog的很眼熟,呵呵
T0: MEM_POOL_BASE: 84368cd8
T0: Initializing memory pool size=01497328 bytes
T0: Press '!' within 3 seconds to enter debugger before INIT


LSI Logic Boot loader


LSI ROC initialization code
VID 1000 DID 79 SSVID 1000 SSID 9261 Rev 05
Frequencies: CPU: 800 Mhz, PLB: 200 Mhz, DDR: 400 Mhz
SysRstSns  80000001 PceMiscCfg 0091c600 PceCfgValid 00000001
SysPllCtrl 8032f561 MemPllCtrl 8030f561
I2C 0 reset!
Mem Dll lock took 11 us
I2C 0 reset!
>> SPD data begin <<
     Memory Type: DDR-2
    Memory Speed: 400 Mhz [2.50ns]
      Data Width: 72 bits
       #RAS Bits: 13
       #CAS Bits: 10
#Banks each chip: 8
      Chip width: x16
  #Banks in DIMM: 1
       DIMM Size: 512MB (1024MB calculated from other SPD data)
     CAS Latency: CL3, CL4, CL5, CL6,
      Registered: No
Voltage Standard: SSTL 1.8
DIMM Config Type: ECC
    SPD Checksum: 0x27 (checksum is Good)
>> SPD data end <<
RAW SPD Data:
00000000: 80 08 08 0d 0a 00 48 00 - 05 25 40 02 82 10 08 00
00000010: 0c 08 78 00 00 00 03 30 - 45 3d 50 3c 28 3c 2d 80
00000020: 17 25 05 12 3c 1e 1e 00 - 06 3c 7f 80 14 1e 00 00
00000030: 00 03 00 00 00 00 00 00 - 00 00 00 00 00 00 13 27
initDDR: SBR is configured for a speed below capabilities of installed DIMM
******** Board = 800 Mhz, DIMM supports 800 Mhz
using CasLat 6
DDR init sequence completed in b us
fifoDelayIndex = 7
gateon[0] complete. 0=8f, 1=92, 2=91, 3=91, 4=8f, 5=91, 6=8f, 7=8f,
gateon[1] complete. 8=8d,
All bytes failed dec.  current: e0
fifo Train(Ecc) failed Bytes 0
fifo Train(Ecc) ecc pat failed Bytes 100
fifo Train(Ecc) test 2 ecc pat failed Bytes 0
Fifo training completed.  rdqs 000 delays: 0=a0 1=a0 2=a0 3=a0 4=a0 5=a0 6=a0 7=a0 8=a0
init ReadEye training dataorEcc 0
ReadEye edge 0 Results
Nib base     Low   High    Avg
00  0054  ffffffca 0027 fffffff9
01  0056  ffffffca 0029 fffffffa
02  0056  ffffffc7 0029 fffffff8
03  0054  ffffffcd 002a fffffffc
04  0054  ffffffc6 0029 fffffff8
05  0057  ffffffcb 002a fffffffb
06  0053  ffffffc3 002d fffffff8
07  0056  ffffffcb 0031 fffffffe
08  0052  ffffffcc 002a fffffffb
09  0055  ffffffc9 0026 fffffff8
0a  0053  ffffffca 002a fffffffa
0b  0056  ffffffca 0024 fffffff7
0c  0053  ffffffc9 002a fffffffa
0d  0055  ffffffc9 002a fffffffa
0e  0056  ffffffc4 002a fffffff7
0f  0058  ffffffc8 002a fffffff9
ReadEye edge 1 Results
Nib base     Low   High    Avg
00  0050  ffffffcb 0025 fffffff8
01  0056  ffffffc4 0026 fffffff5
02  0050  ffffffcb 0026 fffffff9
03  0057  ffffffcd 002a fffffffc
04  0052  ffffffca 0026 fffffff8
05  0055  ffffffcb 002a fffffffb
06  0054  ffffffc8 0026 fffffff7
07  0057  ffffffcb 002a fffffffb
08  004d  ffffffcc 0023 fffffff8
09  0056  ffffffc5 0023 fffffff4
0a  004d  ffffffcb 0026 fffffff9
0b  0056  ffffffcb 002a fffffffb
0c  004f  ffffffc9 0026 fffffff8
0d  0056  ffffffca 0026 fffffff8
0e  0051  ffffffc6 0027 fffffff7
0f  0057  ffffffc8 002d fffffffb
init ReadEye training dataorEcc 1
ReadEye edge 0 Results
Nib base     Low   High    Avg
10  0054  ffffffc9 0028 fffffff9
11  0055  ffffffc9 0028 fffffff9
ReadEye edge 1 Results
Nib base     Low   High    Avg
10  004e  ffffffca 0025 fffffff8
11  0054  ffffffca 0025 fffffff8
Second run of FIFO Delay training.
All bytes failed dec.  current: e0
fifo Train(Ecc) failed Bytes 0
fifo Train(Ecc) ecc pat failed Bytes 100
fifo Train(Ecc) test 2 ecc pat failed Bytes 0
Fifo training completed.  rdqs 000 delays: 0=a0 1=a0 2=a0 3=a0 4=a0 5=a0 6=a0 7=a0 8=a0
Done
Dirty DRAM signature not found.. Cache is not dirty
Verifying TTY history log [addr=0x80100000, 1 MB]: Done
Testing memory [addr=0x0, 1 MB]: Done
Testing memory [addr=0x200000, 510 MB]: Done
SramSignature 0
Scrubbing between DramPersistent and TTY [addr=0x80040000-0x80100000]

loadBios: Images found=3 start=80040000 size=12a00
Scrubbing DramPersistent [addr=0x80000000-0x80040000]
Scrubbing from end of TTY to Disk Cache [addr=0x80200000-0x85800000]
Scrubbing Disk Cache [addr=0x85800000, 424 MB]

LOAD section: src=fe011eee, size=ea8a4, dst=c0800000, mode=1...done
LOAD section: src=fe0fc79b, size=21cd0, dst=c0541400, mode=1...done
LOAD section: src=fe11e474, size=23b1c, dst=80c00000, mode=1...done
LOAD section: src=fe141f99, size=a35, dst=c03fc000, mode=1...done
LOAD section: src=fe1429d7, size=10b, dst=e048c, mode=1...done
stack is c05413f8

T0: LSI ROC firmware
T0: Copyright(C) LSI Corporation, 2010
T0: Firmware version 2.120.183-1415 built on Oct  5 2011 at 12:32:12

T0:  *** HW Encryption Disabled : dcrReg=80000001
T0: setAdapterResetTime: CCR_MISC_CFG 8002ff2c
T0: DRAM_LOCAL_BASE: 80000000
T0: MEM_FIXED_SIZE: a00000
T0: FW_DRAM_REGION_START: 80c00000
T0: FW_DRAM_REGION_SIZE: 4c00000
T0: MEM_POOL_BASE: 84368cd8
T0: Initializing memory pool size=01497328 bytes
T0: Press '!' within 3 seconds to enter debugger before INIT


LSI Logic Boot loader


LSI ROC initialization code
VID 1000 DID 79 SSVID 1000 SSID 9261 Rev 05
Frequencies: CPU: 800 Mhz, PLB: 200 Mhz, DDR: 400 Mhz
SysRstSns  80000001 PceMiscCfg 0091c600 PceCfgValid 00000001
SysPllCtrl 8032f561 MemPllCtrl 8030f561
I2C 0 reset!
Mem Dll lock took 10 us
I2C 0 reset!
>> SPD data begin <<
     Memory Type: DDR-2
    Memory Speed: 400 Mhz [2.50ns]
      Data Width: 72 bits
       #RAS Bits: 13
       #CAS Bits: 10
#Banks each chip: 8
      Chip width: x16
  #Banks in DIMM: 1
       DIMM Size: 512MB (1024MB calculated from other SPD data)
     CAS Latency: CL3, CL4, CL5, CL6,
      Registered: No
Voltage Standard: SSTL 1.8
DIMM Config Type: ECC
    SPD Checksum: 0x27 (checksum is Good)
>> SPD data end <<
RAW SPD Data:
00000000: 80 08 08 0d 0a 00 48 00 - 05 25 40 02 82 10 08 00
00000010: 0c 08 78 00 00 00 03 30 - 45 3d 50 3c 28 3c 2d 80
00000020: 17 25 05 12 3c 1e 1e 00 - 06 3c 7f 80 14 1e 00 00
00000030: 00 03 00 00 00 00 00 00 - 00 00 00 00 00 00 13 27
initDDR: SBR is configured for a speed below capabilities of installed DIMM
******** Board = 800 Mhz, DIMM supports 800 Mhz
using CasLat 6
DDR init sequence completed in b us
fifoDelayIndex = 7
gateon[0] complete. 0=8f, 1=91, 2=91, 3=91, 4=91, 5=91, 6=8f, 7=8f,
gateon[1] complete. 8=8d,
All bytes failed dec.  current: e0
fifo Train(Ecc) failed Bytes 0
fifo Train(Ecc) ecc pat failed Bytes 100
fifo Train(Ecc) test 2 ecc pat failed Bytes 0
Fifo training completed.  rdqs 000 delays: 0=a0 1=a0 2=a0 3=a0 4=a0 5=a0 6=a0 7=a0 8=a0
init ReadEye training dataorEcc 0
ReadEye edge 0 Results
Nib base     Low   High    Avg
00  0055  ffffffcc 0026 fffffff9
01  0054  ffffffcb 002d fffffffc
02  0057  ffffffc5 0026 fffffff6
03  0054  ffffffcd 002c fffffffd
04  0054  ffffffc6 0029 fffffff8
05  0056  ffffffcc 0029 fffffffb
06  0054  ffffffc2 002c fffffff7
07  0056  ffffffcb 002c fffffffc
08  0054  ffffffcc 0025 fffffff9
09  0054  ffffffca 0023 fffffff7
0a  0054  ffffffc6 002a fffffff8
0b  0055  ffffffcc 0026 fffffff9
0c  0054  ffffffc9 0029 fffffff9
0d  0054  ffffffca 0029 fffffffa
0e  0057  ffffffc3 0029 fffffff6
0f  0057  ffffffc9 0029 fffffff9
ReadEye edge 1 Results
Nib base     Low   High    Avg
00  0050  ffffffcd 0025 fffffff9
01  0056  ffffffc4 0028 fffffff6
02  0051  ffffffcc 0028 fffffffa
03  0057  ffffffcd 0029 fffffffb
04  0051  ffffffcb 0029 fffffffa
05  0056  ffffffcc 0028 fffffffa
06  0052  ffffffc7 0029 fffffff8
07  0057  ffffffcb 002c fffffffc
08  004b  ffffffcd 0022 fffffff8
09  0056  ffffffc5 0025 fffffff5
0a  004e  ffffffcb 0022 fffffff7
0b  0057  ffffffcc 0029 fffffffb
0c  004e  ffffffca 0028 fffffff9
0d  0056  ffffffca 0028 fffffff9
0e  0050  ffffffc7 0028 fffffff8
0f  0058  ffffffc9 002c fffffffb
init ReadEye training dataorEcc 1
ReadEye edge 0 Results
Nib base     Low   High    Avg
10  0055  ffffffca 0025 fffffff8
11  0055  ffffffca 0025 fffffff8
ReadEye edge 1 Results
Nib base     Low   High    Avg
10  004d  ffffffca 0025 fffffff8
11  0053  ffffffca 0025 fffffff8
Second run of FIFO Delay training.
All bytes failed dec.  current: e0
fifo Train(Ecc) failed Bytes 0
fifo Train(Ecc) ecc pat failed Bytes 100
fifo Train(Ecc) test 2 ecc pat failed Bytes 0
Fifo training completed.  rdqs 000 delays: 0=a0 1=a0 2=a0 3=a0 4=a0 5=a0 6=a0 7=a0 8=a0
Done
Dirty DRAM signature not found.. Cache is not dirty
Verifying TTY history log [addr=0x80100000, 1 MB]: Done
Testing memory [addr=0x0, 1 MB]: Done
Testing memory [addr=0x200000, 510 MB]: Done
SramSignature 0
Scrubbing between DramPersistent and TTY [addr=0x80040000-0x80100000]

loadBios: Images found=3 start=80040000 size=12a00
Scrubbing DramPersistent [addr=0x80000000-0x80040000]
Scrubbing from end of TTY to Disk Cache [addr=0x80200000-0x85800000]
Scrubbing Disk Cache [addr=0x85800000, 424 MB]

LOAD section: src=fe011eee, size=ea8a4, dst=c0800000, mode=1...done
LOAD section: src=fe0fc79b, size=21cd0, dst=c0541400, mode=1...done
LOAD section: src=fe11e474, size=23b1c, dst=80c00000, mode=1...done
LOAD section: src=fe141f99, size=a35, dst=c03fc000, mode=1...done
LOAD section: src=fe1429d7, size=10b, dst=e048c, mode=1...done
stack is c05413f8

T0: LSI ROC firmware
T0: Copyright(C) LSI Corporation, 2010
T0: Firmware version 2.120.183-1415 built on Oct  5 2011 at 12:32:12

T0:  *** HW Encryption Disabled : dcrReg=80000001
T0: setAdapterResetTime: CCR_MISC_CFG 8002ff2c
T0: DRAM_LOCAL_BASE: 80000000
T0: MEM_FIXED_SIZE: a00000
T0: FW_DRAM_REGION_START: 80c00000
T0: FW_DRAM_REGION_SIZE: 4c00000
T0: MEM_POOL_BASE: 84368cd8
T0: Initializing memory pool size=01497328 bytes
T0: Press '!' within 3 seconds to enter debugger before INIT
T3: One Wire Device detected 170000047b082233
T3: EepromInit: Family=33, SN=22087b040000
T3: One Wire Device detected 170000047b082233
T3: One Wire Device detected 170000047b082233
T3: One Wire Device detected 170000047b082233
T3: PfkStartTrialKeyTimer: Trial Timer started!
T3: Authenticating RAID key: One Wire Device detected 170000047b082233
T3: One Wire Device detected 170000047b082233
T3: Done!
T3: CFGI firmware version 5.0.0.2
T3: Nvdata version 2.09.03-0024 built on Oct 05 2011 at 00:43:21

T3: LOAD section: src=fe560128, size=2e86, dst=fe560058, mode=1...InflatNvdata - tempbuf = 8576d7c0, buf = 857f57d0, len = =8000
T3: InflatNvdata - tempbuf = 857757c0, buf = 857f57d0, len = =8000
T3: InflatNvdata - tempbuf = 8577d7c0, buf = 857f57d0, len = =8000
T3: InflatNvdata - tempbuf = 857857c0, buf = 857f57d0, len = =8000
T3: InflatNvdata - tempbuf = 8578d7c0, buf = 857f57d0, len = =8000
T3: InflatNvdata - tempbuf = 857957c0, buf = 857f57d0, len = =8000
T3: InflatNvdata - tempbuf = 8579d7c0, buf = 857f57d0, len = =8000
T3: InflatNvdata - tempbuf = 857a57c0, buf = 857f57d0, len = =8000
T3: InflatNvdata - tempbuf = 857ad7c0, buf = 857f57d0, len = =8000
T3: InflatNvdata - tempbuf = 857b57c0, buf = 857f57d0, len = =8000
T3: InflatNvdata - tempbuf = 857bd7c0, buf = 857f57d0, len = =8000
T3: InflatNvdata - tempbuf = 857c57c0, buf = 857f57d0, len = =8000
T3: InflatNvdata - tempbuf = 857cd7c0, buf = 857f57d0, len = =8000
T3: InflatNvdata - tempbuf = 857d57c0, buf = 857f57d0, len = =770
T3: done
T3: DM_Cfg_InitConfigPages: Count of binaries found so far countNVDATA=1
T3: DM_Cfg_InitConfigPages: Count of binaries found so far countNVDATA=2
T3: DM_Cfg_InitConfigPages: Count of binaries found so far countNVDATA=3
T3: DM_Cfg_InitConfigPages: Count of binaries found so far countNVDATA=4
T3: DM_Cfg_InitConfigPages: Count of binaries found so far countNVDATA=5
T3: DM_Cfg_InitConfigPages: Count of binaries found so far countNVDATA=6
T3: DM_Cfg_InitConfigPages: Count of binaries found so far countNVDATA=7
T3: DM_Cfg_InitConfigPages: Count of binaries found so far countNVDATA=8
T3: DM_Cfg_InitConfigPages: Count of binaries found so far countNVDATA=9
T3: DM_Cfg_InitConfigPages: Count of binaries found so far countNVDATA=10
T3: DM_Cfg_InitConfigPages: NVDATA page matched
T3: **********************************************************************
T3: iopiSODAlloc: size = 1a4, MemType = 1
T3: **********************************************************************
T3: iopiSODAlloc: size = 1ab0, MemType = 3
T4: Config Pages initialization completed. Persistent Nvdata version = 73015

T4:  SRAM beginning and end for DM is xc0054400 xc0131400

T4: DM PL FRAME POOL INFO: plFrames=c0054400, plNonCritFrames=c00ca400 plCritFrames=c00d2400 iopNonCriticalFrames c00d4400

T4:  Total memory allocated for DM PL Frames is : 84000
T4: PL MID #0: msgNm=00000000, addr=c0054400
T4: Address of dmIoCtx :: xc05eb200
T4: size of MFC Defaults structure in Bytes = 72
T4: EVT#09573-T4:   0=Firmware initialization started (PCI ID 0079/1000/9261/1000)
T4: EVT#09574-T4:   1=Firmware version 2.120.183-1415
T4: I2C 0 reset!
T4: I2Chandle obtained for MUX [0]0x0
T4: I2c 0 mux was reset!
T4: I2C 0 reset!
T4: I2C 1 reset!
T4: I2Chandle obtained for MUX [1]0x10
T4: I2c 0 mux was reset!
T4: I2C 0 reset!
T4: I2C 2 reset!
T4: I2Chandle obtained for MUX [2]0x20
T4: I2c 0 mux was reset!
T4: I2C 0 reset!
T4: SBR: I2Chandle obtained for SBR 21
T4: Raw SBR Image data:
00000000: 61 f5 32 61 f5 30 4f b3 - f8 00 c6 91 00 10 79 00
00000010: 00 00 04 01 00 10 61 92 - 00 00 00 00 00 00 00 00
00000020: 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
00000030: 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
00000040: 00 2c 00 00 00 00 00 00 - 00 00 00 3f 61 f5 32 61
00000050: f5 30 4f b3 f8 00 c6 91 - 00 10 79 00 00 00 04 01
00000060: 00 10 61 92 00 00 00 00 - 00 00 00 00 00 00 00 00
00000070: 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
00000080: 00 00 00 00 00 00 00 00 - 00 00 00 00 00 2c 00 00
00000090: 00 00 00 00 00 00 00 3f - ff ff ff ff ff ff ff ff
000000a0: ff ff ff ff ff ff ff ff - ff ff ff ff ff ff ff ff
000000b0: ff ff ff ff ff ff ff ff - ff ff ff ff ff ff ff ff
000000c0: ff ff ff ff ff ff ff ff - ff ff ff ff ff ff ff ff
000000d0: ff ff ff ff ff ff ff ff - ff ff ff ff ff ff ff ff
000000e0: ff ff ff ff ff ff ff ff - ff ff ff ff ff ff ff ff
T4: DRAM SIZE=512 MB
T4: Init flash timings : FlashTimeNs 78  NvsTimeNs 37
T4: setPhyMap: phy = 0 internalIndex = 0 externalIndex = ff
T4: setPhyMap: phy = 1 internalIndex = 0 externalIndex = ff
T4: setPhyMap: phy = 2 internalIndex = 0 externalIndex = ff
T4: setPhyMap: phy = 3 internalIndex = 0 externalIndex = ff
T4: setPhyMap: phy = 4 internalIndex = 1 externalIndex = ff
T4: setPhyMap: phy = 5 internalIndex = 1 externalIndex = ff
T4: setPhyMap: phy = 6 internalIndex = 1 externalIndex = ff
T4: setPhyMap: phy = 7 internalIndex = 1 externalIndex = ff
T4: setPhyMap: phy = 8 internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 9 internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = a internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = b internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = c internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = d internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = e internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = f internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 10 internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 11 internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 12 internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 13 internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 14 internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 15 internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 16 internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 17 internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 18 internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 19 internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 1a internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 1b internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 1c internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 1d internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 1e internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 1f internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 20 internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 21 internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 22 internalIndex = ff externalIndex = ff
T4: setPhyMap: phy = 23 internalIndex = ff externalIndex = ff

T4: Environment data:
T4: VERSIONS=APP_2.120.183-1415,BIOS_3.23.00_4.11.05.00_0x05080000,HIIM_01.13.00,PCLI_04.04-018:#%00008,BCON_6.0-45-e_40-Rel,NVDT_2.09.03-0024,BTBL_2.02.00.00-0000,BOOT_09.250.01.219
T4: PACKAGE=12.12.0-0073
T4: VALIDATION=GCA_10/05/11_17:36:57

T4: MFC data:
T4:     vendorId/deviceId=1000/0079, subVendorId/subDeviceId=1000/9261, OEM=1, SubOem=0, isRaidKeySecondary=0
T4:     MFCF: clusterDisable=1, disableSAS=0, maxDisks=0, enableRaid6=1, disableWideCache=0
T4:     disableRaid5=0, enableSecurity=1, enableReducedFeatureSet=0
T4:     enableCTIO=1 enableSnapshot=1 enableSSC=1
T4:     MFCD: sasAddr=500605b003a25555, phyPolarity=00 phyPolaritySplit 00
T4:     backgroundRate=30, stripeSize=7(64K), flushTime=4
T4:     writeBack=1, readAhead=2, cacheWhenBBUBad=0, cachedIo=0
T4:     smartMode=0(6), alarmDisable=0, coercion=0(None), zcrConfig=0(Undefined)
T4:     dirtyLedShowsDriveActivity=0, biosContinueOnError=0, spindownMode=0(None)
T4:     allowedDeviceTypes=0(SAS/SATA), allowMixInEnclosure=1, allowMixInLD=1, allowSataInCluster=0
T4:     allowSSDMixInLD=0, allowMixSSDHDDInLD=0
T4:     maxChainedEnclosures=16, disableCtrlR=1, enableWebBios=1, directPdMapping=0, biosEnumerateLds=1
T4:     restoreHotSpareOnInsertion=0, exposeEnclosureDevices=1
T4:     maintainPdFailHistory=1 disablePuncturing=0 zeroBasedEnclEnumeration=0 disableBootCLI=0
T4:     quadPortConnectorMap=0 driveActivityLed=1 disableAutoDetectBackplane=0
T4:     enableLedHeaders=1 useFdeOnly=1 delayPOST=0 enableCrashDump=0 enableLDBBM=0
T4:     allowUnCertifiedHDDs=1 treatR1EAsR10=0, maxLdsPerArray=0, disableOnlineCtrlReset=0
T4:     failPdOnSMARTer=0 nonRevertibleSpares=0,
T4:     snapVDSpace=3, autoSnapVDSpace=8, viewSpace=4
T4:  disablePowerSavings=14 spinDownTime=1e
T4:     enableJBOD=0  ttyLogInFlash=0
T4:     breakMirrorRAIDSupport=0, disableJoinMirror=0  
T4:     enableEmergencySpare=0 useGlobalSparesForEmergency=0 useUnconfGoodForEmergency=0
T4: MFC MFG data:
T4:     date=10/06/11, sn="SV14100495", reworkDate=00/00/00, rev="79B"

T4: can_flush = 0
T4: initFreeDDBs=xorPool c0440000-c0452000 genPool c0404000-c041c000
T4: initBladeSGL c041c000-c043c000

T4: C05FBCD0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 c20c0400
T4: C05FBCF0: c003c000 00000001 ffffffff ffffffff 00000000 00000000

T4: C05FBD08: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 c20c0800
T4: C05FBD28: c003e000 00000001 ffffffff ffffffff 00000000 00000000

T5: Controller Properties: (All values are in hex)
T5:     seqNum=2, predFailPollInterval=12c, intThrottleCount=10
T5:     intThrottleTimeUs=32, rebuildRate=1e, patrolReadRate=1e
T5:     bgiRate=1e, ccRate=1e, reconRate=1e
T5:     cacheFlushInterval=4, spinupDriveCount=4, spinupDelay=2
T5:     clusterEnable=0, coercionMode=0, alarmEnable=1
T5:     disableAutoRebuild=0, disableBatteryWarning=1, eccBucketSize=f
T5:     eccBucketLeakRate=5a0, restoreHotSpareOnInsertion=0
T5:     exposeEnclosureDevices=1, maintainPdFailHistory=1
T5:     disallowHostRequestReordering=0
T5:     abortCCOnError=0, copyBackDisabled=0, SMARTerEnabled=0
T5:     prCorrectUnconfiguredAreas=1, useFdeOnly=1
T5:     disableNCQ=0, SSDSMARTerEnabled=1, SSDPatrolReadEnabled=0
T5:     enableSpinDownUnconfigured=1,   disableSpinDownHS=0,    spinDownTime=1e,        autoEnhancedImport=0, enableSecretKeyControl=0, disableOnlineCtrlReset=0
T5:     enableJBOD=0
T5:     allowBootWithPinnedCache=0
T5:     LoadBalanceEnabled=1, useDiskActivityForLocate=0

T5: useGlobalSparesForEmergency=0, useUnconfGoodForEmergency=0, useEmergencyForSMARTer=0
T5: forceSGPIOForQuadOnly=0
T5:     OnOffProperties=0x000000ac      autoSnapVDSpace=8, viewSpace=4, snapVDSpace=3
T5:     defaultPSPolicy=fe autoPSPolicySupported=0
T5:     maxPSPolicySupported=0 cachedWritesSupported=0
T5:     disablePSTime=0 disablPSInterval=0
T5:     spinupEnclDriveCount=4 spinupEnclDelay=6
T5: I2Chandle obtained for Ni-MH based BBU Charger 1
T5: I2Chandle obtained for Gas Guage 2
T5: I2Chandle obtained for Li-Ion based BBU Charger 3
T5: I2Chandle obtained for Li-Ion based BBU I2C Buffer 4
T5: I2Chandle obtained for impedance Tracking gas guage in iBBU08 5
T5: I2Chandle obtained for GPIO expander in iBBU08 6
T5: I2Chandle obtained for EEprom in expander in iBBU08 7
T5: I2Chandle obtained for I2C_SEP 8
T5: No Battery is Present
T5: PdInit: PD_INFO entries are 0x280 bytes
T5: powerSaveInit: Init structures
T5: EVT#09575-T5: 261=Package version 12.12.0-0073
T5: EVT#09576-T5: 266=Board Revision 79B
T5: ready_list=85800000 (80000 elements)
T5: rebuild_list=85c00000 (8400 elements)
T5: lines_info=85c42000 (12a400 elements)
T5: DISK_CACHE_ADDR=86ee6000
T5: MEM_END_ADDR=9ffffff0

T5: ***** KM_KeyMgmtInitTRNG: size bf saved crc 0 calc crc 0
T5: Setting up TRNG...Done
T6:  Device Module Version 1.1 Date Oct  5 2011 Time 12:28:30
T6: phy = 0, connectorNo = 0, DASEPInfo[i].StartConnectorNo = 0
T6: phy = 4, connectorNo = 1, DASEPInfo[i].StartConnectorNo = 0
T6: QuadMapForDASEP[0] = 3 NoConnector = 2 StartConnectorNo = 0
T6: entry = 0 ConnectorIndex = 0 StartingPhy = 0 StartingSlot = 0
T6: entry = 1 ConnectorIndex = 1 StartingPhy = 0 StartingSlot = 4
T6: QuadMapForDASEP[1] = 0 NoConnector = 0 StartConnectorNo = 255
T6: QuadMapForDASEP[2] = 0 NoConnector = 0 StartConnectorNo = 255
T6: QuadMapForDASEP[3] = 0 NoConnector = 0 StartConnectorNo = 255
T6: QuadMapForDASEP[4] = 0 NoConnector = 0 StartConnectorNo = 255
T6: QuadMapForDASEP[5] = 0 NoConnector = 0 StartConnectorNo = 255
T6: PCI Device Info:
T6:     vendorid = 0
T6:     deviceid = 0
T6:     bar0 = 1
T6:     bar1 = 4
T6:     bar2 = 0
T6:     bar3 = 4
T6:     bar4 = 0
T6: DM_ChipInit: Total chips=1
T6: Chip=0 vendorId 0000 deviceId 0000
T6: Pl firmware version 5.0.32.219
T6: PLMEM INFO : start address = 0xc00d8400  End=0xc0131400
T6:     index 0x00, size 0x00004a80, Attrbute 0x11, Addr 0xc00d8400
T6:     index 0x01, size 0x00000800, Attrbute 0x11, Addr 0xc00dce80
T6:     index 0x02, size 0x00000010, Attrbute 0x11, Addr 0xc00dd680
T6:     index 0x03, size 0x00005d20, Attrbute 0x11, Addr 0xc00dd6a0
T6:     index 0x04, size 0x00001bf0, Attrbute 0x02, Addr 0xc04e33c0
T6:     index 0x07, size 0x00006300, Attrbute 0x02, Addr 0xc04e4fc0
T6:     index 0x08, size 0x00000254, Attrbute 0x12, Addr 0xc00eb2c0
T6:     index 0x09, size 0x0000a500, Attrbute 0x12, Addr 0xc00eb520
T6:     index 0x0a, size 0x00002100, Attrbute 0x12, Addr 0xc00f5a20
T6:     index 0x0c, size 0x00000014, Attrbute 0x12, Addr 0xc00f7b20
T6:     index 0x0d, size 0x00029400, Attrbute 0x12, Addr 0xc00f7b40
T6:     index 0x0e, size 0x00005d20, Attrbute 0x03, Addr 0x857f45e0
T6:     index 0x0f, size 0x0000000c, Attrbute 0x04, Addr 0x857f45a0
T6:     index 0x10, size 0x000003b8, Attrbute 0x03, Addr 0x857f41a0
T6:     index 0x11, size 0x0000c940, Attrbute 0x03, Addr 0x857e7840
T6:     index 0x12, size 0x000000cc, Attrbute 0x03, Addr 0x857e7740
T6:     index 0x13, size 0x000000cc, Attrbute 0x03, Addr 0x857e7640
T6:     index 0x14, size 0x000007bc, Attrbute 0x03, Addr 0x857e6e40
T6:     index 0x15, size 0x00000042, Attrbute 0x03, Addr 0x857e6dc0
T6:     index 0x16, size 0x00000400, Attrbute 0x03, Addr 0x857e69a0
T6:     index 0x17, size 0x00000360, Attrbute 0x03, Addr 0x857e6600
T6:     index 0x18, size 0x00000090, Attrbute 0x13, Addr 0x057e6540
T6:     index 0x19, size 0x00000028, Attrbute 0x03, Addr 0x857e64e0
T6:     index 0x1a, size 0x00000028, Attrbute 0x02, Addr 0xc0520f40
T6:     index 0x1b, size 0x00000018, Attrbute 0x03, Addr 0x857e64a0
T6:     index 0x1c, size 0x00000020, Attrbute 0x03, Addr 0x857e6440
T6:     index 0x1d, size 0x00000074, Attrbute 0x12, Addr 0xc0120f80
T6:     index 0x1e, size 0x00000334, Attrbute 0x14, Addr 0x057e60e0
T6: Total Memory allocated to PL: static = 00048bf4 Dyn=13eee total=5cae2
T6: Current head after allocating PL mem: c0120ff4

T6: SGL FRAME INFO: Start address in SRAM is : xc0121000
T6:      DM_PL_AllocReqFrames: Max SGL frames in SRAM: 104
T6:      From SRAM: SgInIo Frame xd SgInSg Frame x15 TotSg Frames x104 Frame Size x100 sgBaseAddr xc0521000
T6:      Total memory allocated for SGL Frames in SRAM is : x10400
T6:      Allocating left over x1efc SGL frames in DDR at address : x855f64a0
T6:      From DDR: SgInIo Frame xd SgInSg Frame x15 TotSg Frames x1efc Frame Size x100 sgBaseAddr x855f64a0

T6: Waiting for First PL Discovery to complete
T8: Disabling UART for 120s due to discovery
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发表于 2014-5-7 12:42 | 显示全部楼层
坐楼等候 P大光临@per1-q1222
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发表于 2014-5-7 20:11 | 显示全部楼层
@per1-q1222
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 楼主| 发表于 2014-5-7 22:51 | 显示全部楼层
爱喝可乐的小白 发表于 2014-5-7 20:11
@per1-q1222

不太清楚per1-q1222有没有用过这种方式,估计是没有吧,呵呵,不过感觉是诊断LSI阵列卡故障的好方法,官方都说是Reserved for LSI internal use,只是普通用户没有文档支持,不知道如何去使用
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