|
想换个Opteron 1650 o7 X2 u( F# c' E& c
自己用的板子是微星 K8N Neo4 Platinum白金板
& s! I5 u& G% A& jSOCKET 939 K8 的
1 Q+ l& ?+ a N# U9 H到底算可以用不?* X+ G( M8 f/ ^4 m+ ?
去微星网站上看了下CPU支持列表如下:+ B1 [. Y1 i# q* \8 s
! |, i5 U7 r; c2 v I R* G7 w
% q4 n9 O. o. u& O! I" ^
CPU FSB 倍頻 測試結果 6 d) S/ D* l+ [- ^1 z }
Athlon 64 (ClawHammer, 130nm, L2 Cache 512KB)
- l. X$ r0 L. O- E6 HAthlon 64 3500+ (CG version) 200 11 OK / F' j8 l/ L# R) E1 i
Athlon 64 (ClawHammer, 130nm, L2 Cache 1MB)
* D% x! q8 }6 H, ?Athlon 64 4000+ (CG version) 200 12 OK
5 n! d* k3 N2 _9 S6 o8 ]Athlon 64 (Newcastle, 130nm, L2 Cache 512KB)
3 A& w+ x6 x) EAthlon 64 3000+ (CG version) 200 9 OK
* L- n1 p ~- B6 Y/ L& ?Athlon 64 3200+ (CG version) 200 10 OK 8 l! i5 K; T% w' p( H, s# Y
Athlon 64 3400+ (CG version, Hypertransport) 200 11 OK + N! _) J: t7 }8 k
Athlon 64 3500+ (CG version) 200 11 OK
4 o; d2 x6 [6 r& ?# C' nAthlon 64 3800+ (CG version) 200 12 OK 9 J6 s) h5 y% e0 [7 Z
Athlon 64 (Winchester, 90nm, L2 Cache 512KB) - D7 _2 I% M+ A$ F) s
Athlon 64 3000+ (D0 version) 200 9 OK
8 X: s. M+ x; O, T5 [Athlon 64 3200+ (D0 version) 200 10 OK
( e7 X+ A2 M, Z- c6 XAthlon 64 3500+ (D0 version) 200 11 OK 1 U! n- F% \$ z4 y0 i) a$ d
Athlon 64 (Venice, 90nm, L2 Cache 512KB)
/ `/ u# w g8 d8 k% s, sAthlon 64 3000+ (E3 version) 200 9 OK / Y/ j- J, P: Q! Z
Athlon 64 3200+ (E3 version) 200 10 OK / V1 {- [( Q4 I$ d2 h
Athlon 64 3500+ (E3 version) 200 11 OK
6 M; o \2 q- A/ E$ KAthlon 64 3800+ (E3 version) 200 12 OK
& O. A% U' r" B; J6 aAthlon 64 (Venice, 90nm, L2 Cache 512KB)
# L) p2 S: }7 a9 jAthlon 64 3000+ (E6 version) 200 9 OK
5 F! \8 G. q" w" ]" \Athlon 64 3200+ (E6 version) 200 10 OK
t) R3 d% x2 F8 ?6 TAthlon 64 3400+ (E6 version) 200 11 OK
) p& M6 C- X' R U$ H9 _7 _Athlon 64 3500+ (E6 version) 200 11 OK 6 D' X% t4 t! K: f
Athlon 64 3800+ (E6 version) 200 12 OK + v& i3 V" g: o
Athlon 64 (San Diego, 90nm, L2 Cache 1MB)
8 D K8 d" e& V. ?( dAthlon 64 3700+ (E4 version) 200 11 OK $ H4 r( ]" ]- z- s
Athlon 64 4000+ (E4 version) 200 12 OK
# ^1 T4 h$ K8 t8 ` b% t5 F2 hAthlon 64 FX (ClawHammer, 130nm, L2 Cache 1MB)
& W2 N5 c8 S2 {5 n4 DAthlon 64 FX53 (CG version) 200 12 OK * E; N; _; a; E1 B7 j( {
Athlon 64 FX55 (CG version) 200 13 OK
$ y- U: w/ y9 C( @8 |2 O) WAthlon 64 FX (San Diego, 90nm, L2 Cache 1MB)
5 z F6 Q+ W( a/ G" X6 ]6 sAthlon 64 FX-55 (E4 version) 200 13 OK
: s0 Q$ ]$ ?; d3 u$ {; c( p6 oAthlon 64 FX-57 (E4 version) 200 14 OK
; v( n5 O. z( F' B0 Y3 hAthlon 64 X2 Dual-Core (Manchester, 90nm, L2 Cache 2 x 512KB)
. N# I: M2 I* k0 s0 y5 u- |, p0 `4 @Athlon 64 X2 Dual-Core 3800+ (E4 version) 200 10 OK 0 g) b+ M" k* o/ q* I; U
Athlon 64 X2 Dual-Core 4200+ (E4 version) 200 11 OK
) s2 t4 Y. ^' N% Q- t( v' h. T; ]5 MAthlon 64 X2 Dual-Core 4600+ (E4 version) 200 12 OK
$ B. t. R3 ?+ b4 p5 `: n* }Athlon 64 X2 Dual-Core (Manchester, 90nm, L2 Cache 2 x 512KB)
2 |7 R9 h* q$ |3 K& Y8 E) X- W MAthlon 64 X2 Dual-Core 3800+ (E6 version) 200 10 OK 5 @/ i2 {2 ^6 ]* G5 j, e, U
Athlon 64 X2 Dual-Core 4200+ (E6 version) 200 11 OK
8 B3 \0 k; @( d5 g& y: n5 qAthlon 64 X2 Dual-Core 4600+ (E6 version) 200 12 OK - g; L- _$ O' b3 r& `
Athlon 64 X2 Dual-Core (Toledo, 90nm, L2 Cache 2 x 1MB)
2 ^4 ?9 r( L# R& A, HAthlon 64 X2 Dual-Core 4400+ (E6 version) 200 11 OK 9 [9 w% `$ w! a
Athlon 64 X2 Dual-Core 4800+ (E6 version) 200 12 OK |
|