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想换个Opteron 165
, r' l4 w) S( b! _* H自己用的板子是微星 K8N Neo4 Platinum白金板 5 C8 y8 f6 n" y5 Q$ P9 h, R# @
SOCKET 939 K8 的
# k4 V/ b/ |, T2 S到底算可以用不?
. `4 b8 A) x' x9 q1 Z* ^! `; ~去微星网站上看了下CPU支持列表如下:
# @: M9 \* v N3 h! R. R6 l. ]) i3 _# N; |& \
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CPU FSB 倍頻 測試結果 ! ~. y' u h/ v4 C- c, t6 _
Athlon 64 (ClawHammer, 130nm, L2 Cache 512KB) ) p# _7 J. C" t$ w
Athlon 64 3500+ (CG version) 200 11 OK
" E1 d3 \7 |, Y9 z* n1 [, l. cAthlon 64 (ClawHammer, 130nm, L2 Cache 1MB) 2 o r1 P5 k1 S* A
Athlon 64 4000+ (CG version) 200 12 OK 1 n5 C7 |8 n3 T
Athlon 64 (Newcastle, 130nm, L2 Cache 512KB)
/ m' G* l/ ?$ y7 f& i3 DAthlon 64 3000+ (CG version) 200 9 OK $ T* {0 _ S) x. l. H9 u- v
Athlon 64 3200+ (CG version) 200 10 OK
& M" z |9 B' p7 F( B. g' T/ C, _Athlon 64 3400+ (CG version, Hypertransport) 200 11 OK " Y- J/ u; F" g$ V3 f5 @
Athlon 64 3500+ (CG version) 200 11 OK 9 w9 h" K) a6 ?
Athlon 64 3800+ (CG version) 200 12 OK 0 K I. D, g3 l* M* T! l+ g( u
Athlon 64 (Winchester, 90nm, L2 Cache 512KB)
# L$ d4 y% K+ W6 {( iAthlon 64 3000+ (D0 version) 200 9 OK 3 Q1 x6 `9 p4 I; ?- U
Athlon 64 3200+ (D0 version) 200 10 OK
& M. D6 k* \$ ~; o+ \ U- { T' YAthlon 64 3500+ (D0 version) 200 11 OK
5 c2 d3 C$ [! d& y+ }! K" ?Athlon 64 (Venice, 90nm, L2 Cache 512KB)
, Y/ P' O+ I; P" s3 w0 U fAthlon 64 3000+ (E3 version) 200 9 OK
% D. E0 p4 _4 _ ^2 J% {5 oAthlon 64 3200+ (E3 version) 200 10 OK
5 h6 `) g+ C# I9 V! a( aAthlon 64 3500+ (E3 version) 200 11 OK $ K/ l0 S9 r6 g# {
Athlon 64 3800+ (E3 version) 200 12 OK C! f9 d0 @6 ?2 M4 V9 M' w* ]
Athlon 64 (Venice, 90nm, L2 Cache 512KB) $ k' i3 F) q# {& p
Athlon 64 3000+ (E6 version) 200 9 OK
' M! S) H" G% |) O6 z& x8 }Athlon 64 3200+ (E6 version) 200 10 OK
$ E: O- \* `6 tAthlon 64 3400+ (E6 version) 200 11 OK
) C8 c* P0 h7 h3 h1 j: q' R0 z gAthlon 64 3500+ (E6 version) 200 11 OK
' n2 \- a& e( e, x1 [Athlon 64 3800+ (E6 version) 200 12 OK
4 U1 ~" p5 o: B, Q8 m- R+ _" zAthlon 64 (San Diego, 90nm, L2 Cache 1MB) ! {1 j- z% M9 J; U8 r
Athlon 64 3700+ (E4 version) 200 11 OK ' c/ z4 Z- v1 }8 f/ `6 `5 B
Athlon 64 4000+ (E4 version) 200 12 OK ! T# O: g: x0 d* @
Athlon 64 FX (ClawHammer, 130nm, L2 Cache 1MB)
% \# E+ N9 r7 P! nAthlon 64 FX53 (CG version) 200 12 OK
- J) c+ j& P) A3 O( z4 j* `Athlon 64 FX55 (CG version) 200 13 OK
' Y; A ^1 w! _6 A) I! QAthlon 64 FX (San Diego, 90nm, L2 Cache 1MB) ' I/ q$ b8 ~: A4 Y6 w2 p
Athlon 64 FX-55 (E4 version) 200 13 OK
7 D, `" r' S5 |6 ]! x( S3 H- q! bAthlon 64 FX-57 (E4 version) 200 14 OK + o5 }# j: o9 D# m
Athlon 64 X2 Dual-Core (Manchester, 90nm, L2 Cache 2 x 512KB) ) N- R- ^8 h$ x. V) z& `
Athlon 64 X2 Dual-Core 3800+ (E4 version) 200 10 OK ' U! O( k& d( T4 ^/ X
Athlon 64 X2 Dual-Core 4200+ (E4 version) 200 11 OK
! _% j* ^3 x' [' }' UAthlon 64 X2 Dual-Core 4600+ (E4 version) 200 12 OK
6 J4 ?$ Z) V- iAthlon 64 X2 Dual-Core (Manchester, 90nm, L2 Cache 2 x 512KB) 5 `5 \7 v/ H- C2 z2 t8 v! \5 J$ q K
Athlon 64 X2 Dual-Core 3800+ (E6 version) 200 10 OK
& Q) \0 ^; o1 mAthlon 64 X2 Dual-Core 4200+ (E6 version) 200 11 OK 6 w/ K- |: I" o, E# q) p) x
Athlon 64 X2 Dual-Core 4600+ (E6 version) 200 12 OK + O5 D% C- Z1 K
Athlon 64 X2 Dual-Core (Toledo, 90nm, L2 Cache 2 x 1MB) ' X1 x) c% Q, K9 l, t$ Q' H
Athlon 64 X2 Dual-Core 4400+ (E6 version) 200 11 OK " {# q; C# Y. p9 h% S; l
Athlon 64 X2 Dual-Core 4800+ (E6 version) 200 12 OK |
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