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想换个Opteron 1654 v8 \' S' ]7 E4 m4 l0 } K1 y! v; w$ ^
自己用的板子是微星 K8N Neo4 Platinum白金板 ( I% q, ?$ M, p9 M2 \
SOCKET 939 K8 的1 m% Q* G' q# @7 \ X
到底算可以用不?4 {7 V7 a/ W B/ F$ |
去微星网站上看了下CPU支持列表如下:" L7 s- e& F+ [& F- m5 j; }& t
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9 k7 f# J/ T& P+ C# j2 K ~CPU FSB 倍頻 測試結果
" r& w" t& `8 Y7 R. P& r* uAthlon 64 (ClawHammer, 130nm, L2 Cache 512KB)
: ^9 ^# r+ g: |! Z H: m4 wAthlon 64 3500+ (CG version) 200 11 OK
* q7 f# w! z6 @$ A9 J. o! DAthlon 64 (ClawHammer, 130nm, L2 Cache 1MB) - o+ y% P) \ z% S+ a% b8 z# l1 s$ v B% K
Athlon 64 4000+ (CG version) 200 12 OK
/ L6 d! B2 ?# t+ E9 ^# j! NAthlon 64 (Newcastle, 130nm, L2 Cache 512KB)
; q/ [1 u' H8 O; J' UAthlon 64 3000+ (CG version) 200 9 OK
% r" C6 |1 G% K- T& TAthlon 64 3200+ (CG version) 200 10 OK ' d* B" d4 `" {
Athlon 64 3400+ (CG version, Hypertransport) 200 11 OK # ^- b5 X$ f- g
Athlon 64 3500+ (CG version) 200 11 OK & j7 ?1 ?$ l% f0 X& j
Athlon 64 3800+ (CG version) 200 12 OK
3 K: s& E; G$ _* |9 d& iAthlon 64 (Winchester, 90nm, L2 Cache 512KB)
" u9 O( f2 F1 _: ?# j' `$ ?Athlon 64 3000+ (D0 version) 200 9 OK
6 G* G5 u$ X7 q' M8 ~Athlon 64 3200+ (D0 version) 200 10 OK
/ L0 j' t& m- b1 @% ^' D; a* S0 }# y5 yAthlon 64 3500+ (D0 version) 200 11 OK
# `6 F( E. @: e+ c4 e) nAthlon 64 (Venice, 90nm, L2 Cache 512KB) 2 q$ p/ }6 X1 S6 `9 F7 Y
Athlon 64 3000+ (E3 version) 200 9 OK
- I8 w! q! s' |. I8 kAthlon 64 3200+ (E3 version) 200 10 OK
+ J4 x, W/ U+ g5 z7 GAthlon 64 3500+ (E3 version) 200 11 OK ) \% J; h6 F9 J9 g* g7 [* u7 c
Athlon 64 3800+ (E3 version) 200 12 OK
3 Q/ A$ r2 I& d% {/ QAthlon 64 (Venice, 90nm, L2 Cache 512KB) + O$ s5 }0 q% G7 H/ r
Athlon 64 3000+ (E6 version) 200 9 OK 4 ?1 L2 G7 \5 f- [8 }2 L. _" K, P
Athlon 64 3200+ (E6 version) 200 10 OK
. X5 z2 ^8 e& E3 N& l) d6 DAthlon 64 3400+ (E6 version) 200 11 OK 3 A# T( ]3 m) T) h" b8 D
Athlon 64 3500+ (E6 version) 200 11 OK
+ K+ E+ a8 e; c) [0 \Athlon 64 3800+ (E6 version) 200 12 OK
. O- `7 J6 b& Z2 QAthlon 64 (San Diego, 90nm, L2 Cache 1MB)
' }2 d+ e* t7 q! y9 v$ r. DAthlon 64 3700+ (E4 version) 200 11 OK
( B$ A3 p- c% H) T* e9 TAthlon 64 4000+ (E4 version) 200 12 OK
5 y+ c: X$ b; ], r( qAthlon 64 FX (ClawHammer, 130nm, L2 Cache 1MB)
4 H( @9 ~9 e! i4 X4 q6 D3 vAthlon 64 FX53 (CG version) 200 12 OK 7 r" U: a o9 P" B
Athlon 64 FX55 (CG version) 200 13 OK 0 h. X* u! E4 a P, ^( {0 j, A
Athlon 64 FX (San Diego, 90nm, L2 Cache 1MB) 5 z D- g3 \: b) i8 d
Athlon 64 FX-55 (E4 version) 200 13 OK / d& ?# P% x" Y$ q
Athlon 64 FX-57 (E4 version) 200 14 OK 9 I+ e% Q. r$ d! h
Athlon 64 X2 Dual-Core (Manchester, 90nm, L2 Cache 2 x 512KB)
% N+ T, U3 u) l- y6 rAthlon 64 X2 Dual-Core 3800+ (E4 version) 200 10 OK ! T8 L8 ~6 W# W+ W# h
Athlon 64 X2 Dual-Core 4200+ (E4 version) 200 11 OK
* [2 K1 `# W, K" K# p2 c u, PAthlon 64 X2 Dual-Core 4600+ (E4 version) 200 12 OK & p) x* C4 T$ U* s) a
Athlon 64 X2 Dual-Core (Manchester, 90nm, L2 Cache 2 x 512KB) + q% [) J. x4 |; U
Athlon 64 X2 Dual-Core 3800+ (E6 version) 200 10 OK
5 y8 G% R2 Z' ?# x7 U. zAthlon 64 X2 Dual-Core 4200+ (E6 version) 200 11 OK
' m/ \7 n4 Y* K/ p K) G1 \Athlon 64 X2 Dual-Core 4600+ (E6 version) 200 12 OK 4 z4 l$ c. i2 p9 ?
Athlon 64 X2 Dual-Core (Toledo, 90nm, L2 Cache 2 x 1MB) / q) R: ?0 R J! T5 F
Athlon 64 X2 Dual-Core 4400+ (E6 version) 200 11 OK 1 c5 W" v" ?9 U A& H) _; w0 I
Athlon 64 X2 Dual-Core 4800+ (E6 version) 200 12 OK |
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