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想换个Opteron 165( j( p1 Y+ G2 |& X! T
自己用的板子是微星 K8N Neo4 Platinum白金板
5 `; S4 e7 d* n7 G' {SOCKET 939 K8 的" z. d6 R) P+ m4 S, w4 N" V ~% @
到底算可以用不?* ]1 x% Z2 W8 x s7 t
去微星网站上看了下CPU支持列表如下:
0 q( o: v" l9 X% h% f& G: V1 s; B0 e( j! v" b
`1 V# B# L' FCPU FSB 倍頻 測試結果 ( l7 @# i) p! k, R. Z2 B( o: j
Athlon 64 (ClawHammer, 130nm, L2 Cache 512KB)
1 L1 j# r, U' L# n& K+ Y& D" X* FAthlon 64 3500+ (CG version) 200 11 OK
1 K- e/ v3 ]7 Y/ V0 S5 S) _Athlon 64 (ClawHammer, 130nm, L2 Cache 1MB)
! h- D H9 M8 L8 lAthlon 64 4000+ (CG version) 200 12 OK
# o; }" M* F/ \6 v+ W0 p) k; P( ZAthlon 64 (Newcastle, 130nm, L2 Cache 512KB) ; B! l: [% L, U
Athlon 64 3000+ (CG version) 200 9 OK 6 f3 T/ L! W* [( m
Athlon 64 3200+ (CG version) 200 10 OK + _' f# J; `- J W O
Athlon 64 3400+ (CG version, Hypertransport) 200 11 OK 2 | T' s) }7 a
Athlon 64 3500+ (CG version) 200 11 OK ) Y% r+ d3 v8 F7 o* y: D- ^1 _
Athlon 64 3800+ (CG version) 200 12 OK
- w, L6 k3 ~4 y% P2 f: KAthlon 64 (Winchester, 90nm, L2 Cache 512KB) 1 \6 ~0 \+ e3 k3 t4 A) D, |
Athlon 64 3000+ (D0 version) 200 9 OK
/ N$ p# E5 O$ EAthlon 64 3200+ (D0 version) 200 10 OK
! M! l2 P' ]0 M5 aAthlon 64 3500+ (D0 version) 200 11 OK w' |, \ ]: B2 @! c5 X
Athlon 64 (Venice, 90nm, L2 Cache 512KB)
3 Q0 n$ L2 u9 HAthlon 64 3000+ (E3 version) 200 9 OK 1 _0 D+ U6 j7 s* |( @
Athlon 64 3200+ (E3 version) 200 10 OK
, y' {: h' ]9 X. r2 U" ~2 ]Athlon 64 3500+ (E3 version) 200 11 OK
! Y# i; i1 r1 c4 n/ F ?7 K) z7 {Athlon 64 3800+ (E3 version) 200 12 OK
. g2 B5 i m" B& ^0 U- ~ Q( [Athlon 64 (Venice, 90nm, L2 Cache 512KB)
# Q- o* j# j% G; X, m' E4 C. ]Athlon 64 3000+ (E6 version) 200 9 OK
; T; h2 ^# |4 O1 VAthlon 64 3200+ (E6 version) 200 10 OK
. P8 F( y; V+ Y5 v6 kAthlon 64 3400+ (E6 version) 200 11 OK ( H- P2 V4 b" y3 O, x5 d0 ?2 E
Athlon 64 3500+ (E6 version) 200 11 OK 9 p. V( @6 m% ]( C8 \, H5 V' q
Athlon 64 3800+ (E6 version) 200 12 OK
, _5 y0 B0 h# p2 rAthlon 64 (San Diego, 90nm, L2 Cache 1MB)
( V- j; q( H' uAthlon 64 3700+ (E4 version) 200 11 OK ' H4 d4 U- ?6 H: ^4 j* H
Athlon 64 4000+ (E4 version) 200 12 OK 6 L6 d/ T* r, v: `" C" N- C# I
Athlon 64 FX (ClawHammer, 130nm, L2 Cache 1MB) 1 B5 U3 X3 u4 d1 {9 a3 x) \: Y
Athlon 64 FX53 (CG version) 200 12 OK
0 C; t0 m" _$ s% hAthlon 64 FX55 (CG version) 200 13 OK
p& c" |) h L& {Athlon 64 FX (San Diego, 90nm, L2 Cache 1MB)
# v) z6 q" e) t# _4 b7 lAthlon 64 FX-55 (E4 version) 200 13 OK 4 o- ~, ?1 E; i) L f1 |
Athlon 64 FX-57 (E4 version) 200 14 OK
$ Z& {5 u9 ]: \Athlon 64 X2 Dual-Core (Manchester, 90nm, L2 Cache 2 x 512KB) . ^+ g8 B+ i7 W: |! M! i
Athlon 64 X2 Dual-Core 3800+ (E4 version) 200 10 OK , v$ \ d! T& z! ~5 {# E7 p. _
Athlon 64 X2 Dual-Core 4200+ (E4 version) 200 11 OK ( h( z$ O5 g8 P2 K' J0 Y
Athlon 64 X2 Dual-Core 4600+ (E4 version) 200 12 OK
" b5 i9 d/ r0 d) LAthlon 64 X2 Dual-Core (Manchester, 90nm, L2 Cache 2 x 512KB) 4 L% |. F/ k D5 N( P' I+ b
Athlon 64 X2 Dual-Core 3800+ (E6 version) 200 10 OK 5 @% R8 j* \$ w, g$ d0 B
Athlon 64 X2 Dual-Core 4200+ (E6 version) 200 11 OK
G A/ v: R9 {1 {7 a% a6 M1 OAthlon 64 X2 Dual-Core 4600+ (E6 version) 200 12 OK / E$ ^' j5 E6 ~) T- L$ v5 k7 @+ T
Athlon 64 X2 Dual-Core (Toledo, 90nm, L2 Cache 2 x 1MB) 6 _5 \- ^# |5 K5 {* t: i( h# M
Athlon 64 X2 Dual-Core 4400+ (E6 version) 200 11 OK , R9 S+ |) |( Q! g. i
Athlon 64 X2 Dual-Core 4800+ (E6 version) 200 12 OK |
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