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想换个Opteron 165
/ p6 d: Z. y! w, `4 z自己用的板子是微星 K8N Neo4 Platinum白金板 0 F, t, e. N7 h: ]
SOCKET 939 K8 的
5 n( s, q: [4 _1 i0 u& I; e到底算可以用不?
' t+ j! G9 G8 C" v. V+ i/ r- L' r去微星网站上看了下CPU支持列表如下:( ~3 x2 L! V( v% {8 g3 R; v& S
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CPU FSB 倍頻 測試結果 0 W4 k( k1 g8 u7 U1 Y
Athlon 64 (ClawHammer, 130nm, L2 Cache 512KB)
6 s* i0 y9 |; O# hAthlon 64 3500+ (CG version) 200 11 OK
: \- W* Y; W) E5 w' B# z) TAthlon 64 (ClawHammer, 130nm, L2 Cache 1MB)
( q5 H) | z/ U7 Z8 w9 l0 ~Athlon 64 4000+ (CG version) 200 12 OK
2 q; ~9 W; W& L6 f' iAthlon 64 (Newcastle, 130nm, L2 Cache 512KB) 6 M. d3 }8 j" b4 q! K
Athlon 64 3000+ (CG version) 200 9 OK
* g1 V9 l+ a& @7 R! l1 j% O9 Z5 L3 {Athlon 64 3200+ (CG version) 200 10 OK " s. k. U- c' d; ^+ [2 H9 z
Athlon 64 3400+ (CG version, Hypertransport) 200 11 OK , @# y: c1 q1 x
Athlon 64 3500+ (CG version) 200 11 OK : d7 }0 D+ ~' u( s" l
Athlon 64 3800+ (CG version) 200 12 OK ! A' Q) d( G1 ]! v% P5 h. y
Athlon 64 (Winchester, 90nm, L2 Cache 512KB) " s( Z. i6 w# k* ^
Athlon 64 3000+ (D0 version) 200 9 OK
+ l" I$ x+ j$ lAthlon 64 3200+ (D0 version) 200 10 OK
* F9 w9 ^( i8 C, G v' C$ {Athlon 64 3500+ (D0 version) 200 11 OK
% W0 ~3 G9 Y$ F# O5 `& @7 |Athlon 64 (Venice, 90nm, L2 Cache 512KB) $ j: D* G5 H- P# t; v, s1 Q) @
Athlon 64 3000+ (E3 version) 200 9 OK
" B% Z: [- u! ^8 u. h: wAthlon 64 3200+ (E3 version) 200 10 OK / ]9 `% i4 ]9 U; w* _) {
Athlon 64 3500+ (E3 version) 200 11 OK 4 ?5 W/ A9 I+ D9 r& @5 I7 K0 C
Athlon 64 3800+ (E3 version) 200 12 OK
2 }3 s7 X% N/ H Q$ WAthlon 64 (Venice, 90nm, L2 Cache 512KB) * v2 p* c! }$ x' H3 ^' p3 f
Athlon 64 3000+ (E6 version) 200 9 OK : |- }, V( `% h) r- M0 W
Athlon 64 3200+ (E6 version) 200 10 OK
, L* n& u& N3 z& i: ZAthlon 64 3400+ (E6 version) 200 11 OK 7 H$ {" R. {7 Y# y) }' _) A7 I; p
Athlon 64 3500+ (E6 version) 200 11 OK
& ]$ e; B4 Q8 ]2 w) s- N! w! ^" aAthlon 64 3800+ (E6 version) 200 12 OK 4 @$ [ F* s3 I! T2 p
Athlon 64 (San Diego, 90nm, L2 Cache 1MB) ) b5 p' `5 k; @
Athlon 64 3700+ (E4 version) 200 11 OK
?- n6 ^& ?9 e5 l8 T9 ]% A2 n4 C9 RAthlon 64 4000+ (E4 version) 200 12 OK 1 h6 H# v8 ?) _$ O% v2 V
Athlon 64 FX (ClawHammer, 130nm, L2 Cache 1MB) , j6 h3 \* n+ c" N! x; G
Athlon 64 FX53 (CG version) 200 12 OK ! D- ]$ a6 n' ~# b" T X [
Athlon 64 FX55 (CG version) 200 13 OK ( u0 A8 V# T9 W4 \1 v, a
Athlon 64 FX (San Diego, 90nm, L2 Cache 1MB) 4 u+ \& h( h* _$ q( X
Athlon 64 FX-55 (E4 version) 200 13 OK 8 I- i9 c3 y4 _- i9 z
Athlon 64 FX-57 (E4 version) 200 14 OK
/ _! c+ _ U0 [% d9 y3 d( s# PAthlon 64 X2 Dual-Core (Manchester, 90nm, L2 Cache 2 x 512KB) & Y, @1 A& J# k% d4 N7 r9 n1 O3 |1 c
Athlon 64 X2 Dual-Core 3800+ (E4 version) 200 10 OK
: O$ c) X3 N% I5 q) ^) `0 d$ C) EAthlon 64 X2 Dual-Core 4200+ (E4 version) 200 11 OK
: N) \3 P2 [, s4 xAthlon 64 X2 Dual-Core 4600+ (E4 version) 200 12 OK / G3 @. P* z- R. d2 ]5 ^9 Y
Athlon 64 X2 Dual-Core (Manchester, 90nm, L2 Cache 2 x 512KB)
* r8 N3 r W' r/ g- v/ n: GAthlon 64 X2 Dual-Core 3800+ (E6 version) 200 10 OK 6 L' R% ~% }& K5 i7 l
Athlon 64 X2 Dual-Core 4200+ (E6 version) 200 11 OK
. g, H% q/ J: J3 A% {Athlon 64 X2 Dual-Core 4600+ (E6 version) 200 12 OK
8 `# F2 H5 T" Y0 i- HAthlon 64 X2 Dual-Core (Toledo, 90nm, L2 Cache 2 x 1MB)
# N5 Q- s8 H+ jAthlon 64 X2 Dual-Core 4400+ (E6 version) 200 11 OK
4 x; B. V' | k: b, tAthlon 64 X2 Dual-Core 4800+ (E6 version) 200 12 OK |
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