MANUFACTURING DESCRIPTION |
Manufacturer's JEDEC ID Code: | Golden Empire (GEIL) |
Module Manufacturing Location: | 54h |
Module Part Number: | CL5-5-5DDR2-800 |
Module Revision Code: | 4100h |
Module Manufacturing Date: | Week 43, 2007 |
Module Serial Number: | 000008CCh |
LEGITIMATE ARCHITECTURES |
Fundamental Memory Type: | DDR-II SDRAM |
DIMM configuration type: | Non-ECC/Parity |
DIMM type information: | UDIMM (133.35 mm) |
Number of Row Addresses: | 14 |
Number of Column Addresses: | 10 |
Number of DIMM Banks: | 97 |
Module Bank Density: | 512 MB |
Number of Banks on SDRAM Device: | 4 |
Module Data Width: | 64 bits |
Primary SDRAM Width: | x8 |
Error Checking SDRAM Width: | N/A |
Voltage Interface Level: | SSTL 1.8V |
Refresh Rate/Type: | 7.8 us Self Refresh |
DDR SDRAM DIMM Height: | |
TIMING SPECIFICATIONS |
Burst Lengths Supported: | 4, 8 |
CAS# Latencies Supported (tCL): | 3.5T, 3T, 2.5T |
Cycle time at Max CAS Latency: | 2.5 ns |
SDRAM Access from Clock (tAC): | 0.40 ns |
Minimum Clock Cycle at tCL = X - 0.5: | 3.13 ns |
Max Data Access Time at tCL = X - 0.5 (tAC): | 0.50 ns |
Minimum Clock Cycle at tCL = X - 1: | 5.0 ns |
Max Data Access Time at CL = X - 1 (tAC): | 0.60 ns |
Minimum Active to Precharge Time (tRAS): | 37.0 ns |
Minimum RAS to CAS delay (tRCD): | 15.0 ns |
Minimum Row Precharge Time (tRP): | 15.0 ns |
Min Active to Active/Auto Refresh Time (tRC): | 57.0 ns |
Min Auto Ref to Active/Auto Refresh (tRFC): | 105.0 ns |
Min Row Active to Row Active delay (tRRD): | 7.50 ns |
Write Recovery Time (tWR): | 15.0 ns |
Internal write to read command delay (tWTR): | 7.50 ns |
Internal read to precharge command delay (tRTP): | 7.50 ns |
Addr and CMD Input Setup Time Before Clock: | 0.15 ns |
Addr and CMD Input Hold Time After Clock: | 0.22 ns |
Data Input Setup Time Before Clock: | 0.05 ns |
Data Input Hold Time After Clock: | 0.17 ns |
Device Max device cycle time (tCKmax): | 32.0 ns |
Max skew between DQS and DQ signals: | 0.20 ns |
Max Read Data Hold Skew Factor: | 0.24 ns |
Back-to-Back Random Col Access (tCCD): | 0T |
SPD PROTOCOL |
Number of bytes written into SPD: | 128 |
Total number of bytes of SPD: | 256 |
SPD Revision: | 0.0 |
Checksum for Bytes 0-62: | 34h |
SUMMARY SPECIFICATION |
Module Type: DDR-II SDRAM |
Module Size: 49664 MB |
Frequency | tCL | tRCD | tRP | tRAS | tRC | tRFC | tRRD | tWR | tWTR | tRTP | 400 MHz | 3.5 | 6 | 6 | 15 | 23 | 42 | 3 | 7 | 3 | 3 | 233 MHz | 3.0 | 4 | 4 | 9 | 14 | 25 | 2 | 4 | 2 | 2 | 200 MHz | 2.5 | 3 | 3 | 8 | 12 | 21 | 2 | 4 | 2 | 2 |
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