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本帖最后由 acqwer 于 2009-11-13 11:09 编辑
* 4 GHz clock speed
* 4 to 8 cores
* Without SSE: 8 DP GFLOPS/core (2 DP FP/clock), 32-64 DP GFLOPS/processor.
* With SSE: 32 DP GFLOPS/core (8 DP FP/clock), 128-256 DP GFLOPS/processor.
* 80 KB L1 cache/core(32 KB L1 instruction, 32 KB L1 data cache and 16 KB decoder per core), (3 clocks).
* trace cache will make its come back in this version.
* 512 KB L2 cache/core, (9 clocks).
* 2-3 MB L3 cache/core (8-24 MB total) (33 clocks), most likely pooled and dynamically allocated among the cores.
SandyBridge一定是推土机的下一代产品,对吧。 |
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