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基于22nm三栅极工艺技术，由32个X86核心组成运行在1.3G左右，8卡并联理论峰值有7TF双浮点多。
At the International Supercomputing Conference (ISC) 2011 in Hamburg, Germany, Intel unveiled additional details about their Many Integrated Core (MIC) architecture. This technology developed out of the Larrabee GPU project, which was initially meant to be a high-performance x86-based discrete graphics processor. As we all know, Larrabee didn't quite deliver and Intel moved the project into a different direction.
Intel Knights Corner packs around 50 core chip at 22nm, targeting HPC segment
Intel Knights Corner packs around 50 core chip at 22nm, targeting HPC segment
Starting 2010 Intel provided sample boards codenamed Knights Ferry to developers interested in the technology. These weren't offered on the free market, but rather you had to tell Intel that you are interested in using this technology and you better had some good reason doing so. With the upcoming MIC product codenamed Knights Corner this should change.
Intel just announced that the first shipping products will be manufactured at the 22nm node featuring 3D transistors and feature over 50 tiny x86 cores. Intel specifically touts the advantage of using known programming models to program the highly parallel chip. It is possible to have code running both on regular CPU cores and the x86 cores of the accelerator card. A definitive shipping date has not been announced. But if the progress on the 22nm process is any indication, the products can be ready as early as in the first quarter of 2012, but I wouldn't bet on that.
Programming Model for Larrabee Many Core Architecture
Programming Model for Intel's Larrabee Many Core Architecture touts simplicity and easy exchange between processing on main CPU or offloading it to MIC products such as Auburn Isle/Knights Ferry
Knights Ferry Development Board: This is still Larrabee PCB, as Intel removed all display connections
Knights Ferry Development Board: This is still Larrabee PCB, but Intel removed all the display connections and modified cooling
Technical specifications of Knights Corner were unavailable at press time. Knights Ferry evaluation boards feature C0 or D0 stepping Auburn Isle chip, clocked at 1.2GHz and feature 32 cores, each being capable of processing four threads at a time. Auburn Isle also integrated 8MB of coherent cache, one of original reasons why the graphics part of Larrabee architecture did not perform as planned. Knights Ferry board also packs 2GB of GDDR5 memory clocked at 750MHz QDR (3 GT/s). In order to cool down the board, Intel opted for an open end design and a dual-slot cooler.
SGI's view for achieving ExaFLOP perfprmance by 2018
SGI's view for achieving ExaFLOP perfprmance by 2018
Intel has some bold plans with this technology. By 2018 they want to enable ExaScale computing using their MIC architecture. Just to give you a comparison, 1 EFLOP equals 1000 PFLOP. The fastest supercomputer, whi**as also been announced at the ISC 2011 in Hamburg is now the K Computer located at the RIKEN Advanced Institute of Computational Science in Japan delivering 8.16 PFLOPs of Linpack performance.
Intel Knights Ferry Demonstrations at ISC 2011
Intel Knights Ferry Demonstrations at ISC 2011: eight Auburn Isle chips at 1.2GHz yield 7.4TFLOPS of peak computing performance
On ISC 2011, Intel is demonstrating the Knights Ferry boards in single and eight board configuration, demonstrating how 256 MIC cores reach 7.4TFLOPS of peak performance. While this is not as impressive as it seems at first - NVIDIA is demonstrating eight Tesla M2090 boards reaching 10.48 TFLOPS (4096 cores at 1.3GHz) - bear in mind that a mass production Knights Corner board will feature a 22nm silicon with 40% more cores than Auburn Isle, as well as significantly higher clock.
All in all, HPC space in 2012 will really heat up with the arrival of MIC silicon from the market leader.
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发表于 2011-6-21 22:29
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