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其实,翻译比较烂是真的:wacko:
原文:
5.2 An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
2:00 PM
S. Vangal1, J. Howard1, G. Ruhl1, S. Dighe1, H. Wilson1, J. Tschanz1, D. Finan1, P. Iyer2,
A. Singh2, T. Jacob2, S. Jain2, S. Venkataraman2, Y. Hoskote1, N. Borkar1
1Intel, Hillsboro, OR
2Intel, Bangalore, India
A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10×8 2D array
of floating-point cores and packet-switched routers, operating at 4GHz. The 15-FO4
design employs mesochronous clocking, fine-grained clock gating, dynamic sleep
transistors, and body-bias techniques. The 65nm 100M transistor die is designed to
achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
以及
5.4 An Integrated Quad-Core OpteronTM Processor
3:15 PM
J. Dorsey1, S. Searles1, M. Ciraula1, E. Fang2, S. Johnson1, N. Bujanos1, R. Kumar2,
D. Wu1, M. Braganza1, S. Meyers1
1AMD, Austin, TX
2AMD, Sunnyvale, CA
An integrated quad-core x86 processor is implemented in a 65nm 11M SOI CMOS
process. Based on an enhanced OpteronTM core, the SoC-developed processor employs
power- and thermal-management techniques throughout the design. The SRAM cache
designs target process variation considerations and future process scalability. A
DDR2/DDR3 combo-PHY and HT3 I/Os provide high-bandwidth interfaces. |
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