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想换个Opteron 165. c" K3 |/ c2 K3 U
自己用的板子是微星 K8N Neo4 Platinum白金板
( K, V% C0 [* K) T' R- q0 }SOCKET 939 K8 的+ R4 ^& l- F" R& B
到底算可以用不?/ k# H7 N/ ^! u
去微星网站上看了下CPU支持列表如下:% r" y! P A4 T! o9 I4 n3 U, k3 g4 @
7 E9 f+ ?/ }4 E0 j
% z, u/ B$ k- s% GCPU FSB 倍頻 測試結果 , g+ P% \! B7 S8 J2 M
Athlon 64 (ClawHammer, 130nm, L2 Cache 512KB)
6 a3 N; `: ~5 W( R& q# Q6 OAthlon 64 3500+ (CG version) 200 11 OK
( K* B3 P1 c" R6 P5 l. |Athlon 64 (ClawHammer, 130nm, L2 Cache 1MB) 0 d/ B; t6 K6 z" J% w, @
Athlon 64 4000+ (CG version) 200 12 OK 0 T% d2 E( y5 W. d- ?" R
Athlon 64 (Newcastle, 130nm, L2 Cache 512KB) 4 X/ a6 _9 C6 g
Athlon 64 3000+ (CG version) 200 9 OK
! B8 F/ H) w. m$ I7 C; MAthlon 64 3200+ (CG version) 200 10 OK
, W3 s S, V" g2 ?7 t0 PAthlon 64 3400+ (CG version, Hypertransport) 200 11 OK
5 c; H( b( ?& b% ?, a8 CAthlon 64 3500+ (CG version) 200 11 OK & w( f6 N, D- z( A
Athlon 64 3800+ (CG version) 200 12 OK
3 C6 X" ]7 N6 ~/ B7 y# [Athlon 64 (Winchester, 90nm, L2 Cache 512KB) ! k2 R( P, a- q& B
Athlon 64 3000+ (D0 version) 200 9 OK + Z. A6 I1 \+ y2 P1 V7 e
Athlon 64 3200+ (D0 version) 200 10 OK
! }) c" B4 n) WAthlon 64 3500+ (D0 version) 200 11 OK 9 g% R0 D ^5 _- O- V$ _- V% c( X. O, a
Athlon 64 (Venice, 90nm, L2 Cache 512KB) % r- B5 b4 x! Z
Athlon 64 3000+ (E3 version) 200 9 OK
7 ]+ n. N% c* M$ L( ]- `( ?$ J6 ]1 ~Athlon 64 3200+ (E3 version) 200 10 OK
+ o, [ A% R9 l; [) l8 VAthlon 64 3500+ (E3 version) 200 11 OK 4 u" n: J5 l: m
Athlon 64 3800+ (E3 version) 200 12 OK
, C5 J# y; y- P0 o W/ ^, Y: QAthlon 64 (Venice, 90nm, L2 Cache 512KB) 6 V t! M8 @( I' |! D
Athlon 64 3000+ (E6 version) 200 9 OK
?. V; v$ H& |) ?' x5 O9 pAthlon 64 3200+ (E6 version) 200 10 OK ) m) M# n6 H, u# L6 K; o6 L
Athlon 64 3400+ (E6 version) 200 11 OK 3 O5 F6 k! J1 _9 D2 h
Athlon 64 3500+ (E6 version) 200 11 OK
) F; X) t+ X3 d. PAthlon 64 3800+ (E6 version) 200 12 OK
1 D! T3 \, G$ c2 JAthlon 64 (San Diego, 90nm, L2 Cache 1MB)
, d% w# @5 J3 C- xAthlon 64 3700+ (E4 version) 200 11 OK " b2 Y- s; p( a4 s7 u5 i7 B
Athlon 64 4000+ (E4 version) 200 12 OK
( s* c3 R8 U4 e' K1 x1 T% e' pAthlon 64 FX (ClawHammer, 130nm, L2 Cache 1MB) 8 E' A7 v' g& p( x
Athlon 64 FX53 (CG version) 200 12 OK
9 s4 r* ] y$ { D+ X: k# UAthlon 64 FX55 (CG version) 200 13 OK
" Q# r: Q/ T$ T! n4 Z0 Q7 fAthlon 64 FX (San Diego, 90nm, L2 Cache 1MB) y7 u1 _1 _1 ^2 t
Athlon 64 FX-55 (E4 version) 200 13 OK
2 e- X- r) @1 [; z+ dAthlon 64 FX-57 (E4 version) 200 14 OK
& e/ G3 V& V; AAthlon 64 X2 Dual-Core (Manchester, 90nm, L2 Cache 2 x 512KB)
9 T8 J2 m2 z; d% sAthlon 64 X2 Dual-Core 3800+ (E4 version) 200 10 OK
) o$ R% f$ ]- f0 e' ?# l2 iAthlon 64 X2 Dual-Core 4200+ (E4 version) 200 11 OK 9 R0 G4 o, q+ o
Athlon 64 X2 Dual-Core 4600+ (E4 version) 200 12 OK
) v. @0 k/ ^& w4 ]! J. N/ YAthlon 64 X2 Dual-Core (Manchester, 90nm, L2 Cache 2 x 512KB) & k7 \9 E4 e2 _6 X0 }2 h& L
Athlon 64 X2 Dual-Core 3800+ (E6 version) 200 10 OK
, ?2 `0 X9 ?- v* Y* Y/ t) TAthlon 64 X2 Dual-Core 4200+ (E6 version) 200 11 OK ; j+ C* Z% |) _ x$ z9 M T1 D
Athlon 64 X2 Dual-Core 4600+ (E6 version) 200 12 OK 3 _! X/ j- K, A/ {9 X- z, m
Athlon 64 X2 Dual-Core (Toledo, 90nm, L2 Cache 2 x 1MB) * j+ ~" p" b$ b1 L" G% o9 g g3 M- S
Athlon 64 X2 Dual-Core 4400+ (E6 version) 200 11 OK + G; H1 W: P% ~3 m- ?
Athlon 64 X2 Dual-Core 4800+ (E6 version) 200 12 OK |
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