HASWELL UPDATE

PRAM

Haswell is expected to have the following features:[1][4]

22 nm process.
14 stage pipeline.
Up to 8 cores by default.
An entirely new cache design.
Advanced power saving mechanisms.
Possible on-package vector coprocessors.
The addition of fused multiply-add (FMA) instructions.
There is a chance that it will be designed for DDR4 as production timings are quite close to each other.
128 kb L1 cache per core (64 kb data + 64 kb instruction), 4-way associativity.
1 MB L2 cache per core, 4-way associativity.
Up to 16 MB L3 cache shared by all cores, 8-way associativity.

000000yyy

这是哪国文字

kinno

默认就8核心，全新的缓存设计，值得期待啊

amd```fans

8 cores那是Up to 8 cores by default吧
只能说有默认8核的可能性

zaknafein

有种一年前就看过了的感觉

Edison

wiki 上的啦。

the_god_of_pig

YY的吧..

jason_sean

缓存和INTEL以往不大对路哦  全新设计？

李主任

star781230 发表于 2011-1-21 19:48
一个个拆成字母我都认识，连一起就不知道路

你不错啦，认识这么多字母，我也就认出来一个A，还有一个V。

kinno

pcinlife达人辈出～～～～～～