推土机架构优化指南中的亮点

Edison

1.6.4 Instruction Fetching Improvements
While previous AMD64 processors had a single 32-byte fetch window, AMD Family 15h processors have two 32-byte fetch windows, from which four µops can be selected. These fetch windows, when combined with the 128-bit floating-point execution unit, allow the processor to sustain a fetch/dispatch/retire sequence of four instructions per cycle.
(page 25)

1.6.6 Notable Performance Improvements
Several enhancements to the AMD64 architecture have resulted in significant performance improvements in AMD Family 15h processors, including:
• Improved performance of shuffle instructions
• Improved data transfer between floating-point registers and general purpose registers
• Improved floating-point register to floating-point register moves
• Optimization of repeated move instructions
• More efficient PUSH/POP stack operations
• 1-Gbyte paging
(page 26)

2.1 Key Microarchitecture Features
AMD Family 15h processors include many features designed to improve software performance. The internal design, or microarchitecture, of these processors provides the following key features:
• Integrated DDR3 memory controller with memory prefetcher
• 64-Kbyte L1 instruction cache and 16-Kbyte L1 data cache
• Shared L2 cache between cores of compute unit
• Shared L3 cache compute units on chip (for supported platforms)
• 32-byte instruction fetch
• Instruction predecode and branch prediction during cache-line fills
• Decoupled prediction and instruction fetch pipelines
• Four-wayAMD64 instruction decoding (This is a theoretical limit. See section 2.3 on page 31.)
• Dynamic scheduling and speculative execution
• Two-way integer execution
• Two-way address generation
• Two-way 128-bit wide floating-point execution
• Legacy single-instruction multiple-data (SIMD) instruction extensions, as well as support for XOP, FMA4, VPERMILx, and Advanced Vector Extensions (AVX).
• Superforwarding
• Prefetch into L2 or L1 data cache
• Deep out-of-order integer and floating-point execution
• HyperTransport™ technology
(page 30)

The minimum branch misprediction penalty is 20 cycles in the case of conditional and indirect branches and 15 cycles for unconditional direct branches and returns.
(page 34)

yuhiyu

抱着求知欲进来，自插双目怀恨出去

抢钱袋鼠

额，e文不认识我

李主任

抱着求知欲进来，自插双目怀恨出去

Prescott

都是Improvements{lol:]

东方未明

好 就看实际表现有没有说的这么牛

kobe606

只希望四核的在游戏方面能干过2100~

Prescott

kobe606 发表于 2011-7-17 16:30
只希望四核的在游戏方面能干过2100~

游戏就不要想了，必然残废。还不如去买APU。

红发IXFXI

抱着求知欲进来，自插双目怀恨出去

ppzhong

抱着求知欲进来，自插双目怀恨出去{cry:]

zidane1980

when combined with the 128-bit floating-point execution unit, allow the processor to sustain a fetch/dispatch/retire sequence of four instructions per cycle.

• Four-wayAMD64 instruction decoding (This is a theoretical limit. See section 2.3 on page 31.)

把section 2.3 on page 31.这个也放出来看看吧

山中小子

抱着求知欲进来，自插双目怀恨出去{:5_213:}

OPPY

如果我说优化好的推土机是秒杀2600的存在大家  会 pen 我 么{lol:]

zidane1980

OPPY 发表于 2011-7-17 17:14
如果我说优化好的推土机是秒杀2600的存在大家  会 pen 我 么

AMD已经心有余而力不足了
很多设想出来的东西都有机会优化但是都做得不好
如果把推土机架构授权给intel自行修改，秒杀2600应该没多大问题

scim

zidane1980 发表于 2011-7-17 17:04
when combined with the 128-bit floating-point execution unit, allow the processor to sustain a fetch ...

2.3Superscalar Processor
The AMD Family 15h processor is an aggressive, out-of-order, superscalarprocessor. It can fetch, decode, and issue up to four instructions per cycle using decoupled fetch and branch prediction units and three independent instruction schedulers, consisting of two integer schedulers and one floating-point scheduler.
These processors can fetch 32 bytes per cycle and can scan two 16-byte instruction windows for up to four micro-ops, which can be dispatched together in a single cycle. The actual number of micro-ops that are dispatched may be lower, depending on a number of factors, such as decode limits like the number of loads and stores which can issue together and whether instructions can be broken up into 16-byte windows. The processors move integer instructions through the replicated integer clusters and floating point instructions through the shared floating point unit (FPU), as shown in Figure 1. on page 32.

zidane1980

scim 发表于 2011-7-17 17:28
2.3Superscalar Processor
The AMD Family 15h processor is an aggressive, out-of-order, superscalar ...

:loveliness:

阿土来了

看不懂呀．试试去自动翻译下．

阿土来了

1.6.4指令获取的改进
虽然以前的AMD64处理器有一个32字节读取窗口，AMD家庭15H处理器有两个32字节的取窗口，从中可以选择四个μops。这些提取的窗口，与128位浮点执行单元相结合，让处理器保持了百分之四周期指令获取/调度/退休序列。
（第25页）

1.6.6显着的性能改进
AMD64架构的几项改进，导致AMD家庭15H处理器，包括显着的性能改进：
•改进的性能洗牌说明
•改进的浮点寄存器和通用寄存器之间的数据传输
•改进的浮点寄存器，浮点寄存器移动
•优化的重复移动指令
•更有效的PUSH / POP堆栈操作
•1 GB的分页
（第26页）

2.1主要的微体系结构特点
AMD家庭15H处理器包括许多功能，旨在改善软件的性能。这些处理器的内部设计，或微架构，提供了以下主要特点：
•集成DDR3内存控制器，内存预取
•64 KB的L1指令缓存和16 KB的L1数据高速缓存
•共享二级缓存的计算单元之间的核心
•共用L3缓存计算单元芯片（支持的平台）
•32字节的取指令
•指​​令predecode和分支预测在缓存线填充
•解耦预测和指令获取管道
•四wayAMD64指令解码（这是一个理论极限。参见第31页第2.3节。）
•动态调度和投机执行
•双向整数执行
•双向地址生成
•双向128位宽的浮点执行
•传统的单指令多数据（SIMD）指令扩展，以及支持XOP，FMA4，VPERMILx，和高级矢量扩展（AVX）。
•Superforwarding
•预取到L2或L1数据高速缓存
•深出序整数和浮点执行
•的HyperTransport™技术
（第30页）

最小的分支预测错误的刑罚是20个周期的有条件的和间接的分支机构和无条件的直属分公司，并返回15个周期的情况下。
（第34页）

cobra_woo

拖拉机啊 都等着下锅