POPPUR爱换

 找回密码
 注册

QQ登录

只需一步,快速开始

手机号码,快捷登录

搜索
查看: 8599|回复: 22
打印 上一主题 下一主题

DAC与Jitter

[复制链接]
跳转到指定楼层
1#
发表于 2007-2-5 16:37 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
本来打算上解码器的。 但是想了想spdif的jitter。 还是算了吧。 不知道哪个spdif的解调芯片可以再生出spdif调制时候的clock。这样的话就不会有什么jitter了。
% v# N2 N; ^% M5 _% D不过以后有时间的话可以考虑一下自己写个fpga来把spdif信号中的时钟提取出来,现在对spdif还不了解,不知道是不是可行。6 [4 b9 v, T" {  o
. @, g3 h& ~% r$ \9 D
其实jitter是数字音频的最大杀手。" P$ b) @; s0 i# v; u" A
录音时,ADC和CD母盘刻录机的时钟不同。这就引入了第一道jitter.
: O2 r. q% _2 J9 F关键是在回放端的jitter怎么来避免。其实,现在的CD光驱基本上都支持raw read。所以原则上可以抓出完美的wave file。只要dsp和dac之间完全同步就不会有jitter了
2#
发表于 2007-2-5 17:25 | 只看该作者
JITTER是不可能完全避免di
+ C4 I+ t# y$ j. q# X6 n只能通过高精度的时钟来改善
回复 支持 反对

使用道具 举报

3#
发表于 2007-2-5 17:34 | 只看该作者
CD盘本身结构也无法避免jitter
+ ~8 M2 p, a/ m0 x  G0 H; q老了,N年没仔细研究技术了:unsure:
回复 支持 反对

使用道具 举报

4#
发表于 2007-2-5 17:35 | 只看该作者
沙发板凳地毯都是我坐啊:p
回复 支持 反对

使用道具 举报

5#
 楼主| 发表于 2007-2-5 17:49 | 只看该作者
时钟的jitter可以用温控晶振来极大的改善。主要的jitter是来自于非同步的时钟。
回复 支持 反对

使用道具 举报

6#
 楼主| 发表于 2007-2-5 18:02 | 只看该作者
原帖由 nocturne 于 2007-2-5 17:34 发表0 D: E4 u  i) ^/ ^0 \: n
CD盘本身结构也无法避免jitter# P& p+ Q4 ]" r/ s5 v" w4 X" T5 h/ d7 Y
老了,N年没仔细研究技术了:unsure:
! o. c% I( v( Q' p1 t$ {% E% ^- t* C
好像有些超高档的CD的转盘和DAC之间有专门的时钟同步机制的
回复 支持 反对

使用道具 举报

7#
发表于 2007-2-5 18:40 | 只看该作者
原帖由 zifzhu 于 2007-2-5 18:02 发表0 k) o9 _* {( ]$ D, \+ x

! a, Q! t- N6 k7 X2 d好像有些超高档的CD的转盘和DAC之间有专门的时钟同步机制的

! a! v& Z1 F* {7 S8 EN年前下了一些JITTER的PDF,不过现在都忘记了
& b9 n% I' W( Y0 @$ X; T# q你搜索看看:huh:
回复 支持 反对

使用道具 举报

8#
发表于 2007-2-5 19:01 | 只看该作者
LZ有些偏执了吧
回复 支持 反对

使用道具 举报

9#
发表于 2007-2-5 22:42 | 只看该作者
没的好大的影响。我都把他省略在我的HIFI本本上。
回复 支持 反对

使用道具 举报

10#
发表于 2007-2-6 00:46 | 只看该作者
有点累,:( :(
回复 支持 反对

使用道具 举报

11#
发表于 2007-2-6 00:50 | 只看该作者
印象中有人说过接收端可以通过PLL电路来校正JITTER的
+ n$ a4 e: h8 C/ @' d5 V' f9 s也有人说过高档的外置DAC不用考虑输出端的JITTER情况
回复 支持 反对

使用道具 举报

12#
发表于 2007-2-6 01:36 | 只看该作者
原帖由 酷风 于 2007-2-6 00:50 发表2 o4 ?5 m1 y; z$ G3 w5 l
印象中有人说过接收端可以通过PLL电路来校正JITTER的' C) C6 _" J4 y% V! h# i- b
也有人说过高档的外置DAC不用考虑输出端的JITTER情况
  q' A. O7 _! y0 b
: v# \' K1 W3 _0 b, K
/ M( N! o# Z- i# g9 |
常用的接收IC如CS8412就有两种工作模式: 直接使用从S/PDIF信号中恢复的时钟,或使用独立时钟。: x( R( n7 Z' U0 a% _2 g. |

0 H2 k, S6 h, _3 u上图

本帖子中包含更多资源

您需要 登录 才可以下载或查看,没有帐号?注册

x
回复 支持 反对

使用道具 举报

13#
发表于 2007-2-6 01:54 | 只看该作者
见过有几款 m-audio 的音频 IO 有专门接口可以同步clock 的
回复 支持 反对

使用道具 举报

14#
 楼主| 发表于 2007-2-6 09:49 | 只看该作者
其实现在想想,CS8414恢复出来的时钟也会有蛮大的抖动的。
0 V" A. N# I+ }% K+ t( N8 a应该是加一个异步fifo的话就可以彻底解决问题了。这样DAC就可以完全依赖于自己的时钟。不必考虑同步问题了。
$ C# b9 z' `! \( @5 A! x. T不过两者的频率一样,比如spdif出来的时钟是44.099k而DAC的时钟是44.1001k的话,fifo就会欠载。那个也会有一些影响。虽然可以把DAC的时钟调慢点,比如44.050k,但总是有点别扭。4 }$ s& w) r+ K; Q0 r6 v! q
想来想去。现在的音频数字接口不能符合hi-fi的要求。
回复 支持 反对

使用道具 举报

lianghua 该用户已被删除
15#
发表于 2007-2-6 10:00 | 只看该作者
提示: 作者被禁止或删除 内容自动屏蔽
回复 支持 反对

使用道具 举报

16#
发表于 2007-2-6 11:53 | 只看该作者
音频数字接口不能符合hi-fi的要求?
/ ~0 _- c' q4 k$ s% X9 R6 \6 y从何得出的结论?
回复 支持 反对

使用道具 举报

17#
发表于 2007-2-6 13:17 | 只看该作者
原帖由 gzXW 于 2007-2-6 01:36 发表
5 s; Z3 y* }% c# A) T( @0 a8 t5 \) T, k% a& N* k1 k/ @
8 }; c) e# n) Y$ P" l6 k6 i  `
, Z2 A: r0 n' G: N6 l$ i5 C
常用的接收IC如CS8412就有两种工作模式: 直接使用从S/PDIF信号中恢复的时钟,或使用独立时钟。
. ~$ ?1 ]" [. `2 j9 Z- {  X
% |2 J0 Z; r8 c0 G* f上图
7 Y3 F. r8 ^) k" o# V# p# g' [2 n
使用优质的独立时钟能否基本消除jitter?
回复 支持 反对

使用道具 举报

18#
发表于 2007-2-6 13:45 | 只看该作者
这机器有相关的介绍:: D0 s% ^$ t, u" e! ~
   
7 k/ Y" q8 Z; s( k4 _0 ]
5 ~; l1 o) i% l3 e" r0 d, M* g/ L; _Theta Generation VIII DAC/Preamplifier
6 K+ O+ v/ B' B8 H% c# \9 c9 l' y0 K2 c* Y
Specifications:/ {$ {9 a% D. t, u* @
6 |# g  b( ]- Z! G- s, j
● Digital inputs: 2 RCA, 1 BNC, 1 AES/EBU, 2 optical (1 Toslink, 1 optional AT&T)6 w3 E# @3 v) r; ], i; k% H
● Analog Inputs: 1 stereo pair on single-ended RCA jacks, 1 stereo pair on balanced XLR jacks
; C9 L( b  z1 n! y7 p& a9 w( B● Input Impedance: 10 K ohms
" O' u$ Y3 O, r  {. |● Frequency response: DC - 20 KHZ ±.2dB
5 t* B, t6 F* h! K  V● THD+Noise: <0.0005% @3VRMS in and out, balanced/ ^0 X$ @3 d9 p, F
● Dynamic Range: 125dB ref 18VRMS Bal, V+ a  ]; |! O% c
● Signal to Noise Ratio: 125dB ref 18VRMS Bal
5 w; K+ N8 F* j: P, P* z7 m. J● All DSP processing is 24-bit with 56-bit accumulator& M3 W, [) j% Z) M4 E
● D/A Conversion: 24-bit Ladder (8x oversampling); 2 DACs per channel for differential operation- R# W& ^8 O4 q3 R
● Volume Control: Proprietary switched resistor network in the analog domain
/ V7 f& w: f6 s# @1 Y# `● Digital Filter: 8x oversampling proprietary FIR filter running on Motorola 56362 DSP. }( J3 ?- a( z
● Size: 17 5/8” W x 5” H x 17 3/4” D6 m1 Y& N( \6 m
● Weight: 29 lbs
; s! U1 E. O! |7 z% U● MSRP: $10,000 USA1 F2 o; {4 x* u# o

& _9 v8 t3 o& g# Y
9 |+ E- K! \9 i% Z+ J& c
: \0 G. T# h: l3 m
% o$ o6 p$ Y: b# w* D
  1. Notes by Colin Miller: The rest of the industry calls this a Phase Lock Loop (assuming it is similar), operating with a healthy FIFO buffer to reclock the data, or simply reclock it completely without the PLL (a la Meridian) and attenuate if not eliminate jitter, but 'Jitter Jail' is a snazzier name. It may be that the Theta can alternate between these two methods, but it all boils down to a FIFO buffer on the input, and a new clock feeding information to the DAC process.# q1 J. o" \  m; F. @' y, x, G& G3 a
  2. 2 Z# Y- I- ?2 V
  3. Jitter is a timing error, an error in data rate, either over a very short time, or a very long time. Short periods of data rate error (too close together for a few samples, too far for a few more, etc.) are high-frequency jitter. Long periods of data rate error (too close for very many samples, gradually shifting to too far for many more, and so
    . q, I( w; e7 F5 }. Q3 j: P
  4. forth) are low frequency jitter. The only way to correct the error is to correct the timing. The only way to correct the timing is to space the data evenly at either a derived rate, or a known rate. The only way to do this is with some working room, which requires an input buffer, and then you can do what needs to be done, reclock it to the most uniform (evenly spaced) and preferably correct data rate.
    ) o6 b1 Y2 z" a- M: F- p
  5. ) M, ^# @+ ]% Z' `7 A& M
  6. In a perfect world, jitter would be no issue at all. In a next to perfect world, the DAC device would control the transport device's servo-controller that determines the data rate, and the only clock would be the master clock that times the DAC process, and so jitter would be very easily avoided with a small FIFO. That has yet to happen, to my knowledge.# [0 z% {& k( @0 a$ k
  7. 0 h3 s/ w+ ]6 H+ d9 Z! `
  8. In a world almost as perfect as that, you have a FIFO buffer at the input, the DAC device figures out the rate by looking at the data, and reclocks the data completely independently of the incoming rate that would be carrying the jitter. In this scenario, the only jitter possible is that of the DAC's own clock itself, and any jitter prior to that is completely and utterly irrelevant, with one exception. If the error is of low frequency, i.e., goes too fast for awhile, then slows down for awhile, or as a most extreme example of the lowest frequency jitter, spits CD information out at 44,003 samples/second instead of 44,100 samples per second, you'll have buffer over- or underrun, in which case you either get dropouts, no sound, or a really nasty mess of a sound when the DAC tries to resynchronize with the rate. From the comment that your DVD player doesn't work with the "Jitter Jail," I'd guess that they're going this route for higher quality digital sources and that your DVD player is a particularly poor one.  Stacey had this problem with his Meridian anti-jitter reclocking circuitry when he used a particular DVD player with the AC power, but it worked fine with the onboard battery power supply or when he used his Power Plant. He had to set his unit to operate in the more standard PLL with that source.
    9 b' z. x" c8 u" {
  9. - ~* g" ]/ n* p. R
  10. The above illustrates why most of the industry resorts to a PLL, or Phase Lock Loop. This uses the same FIFO buffer, and attempts to smooth the data rate. It'd be like having a bunch of unruly school kids come in clumps through the gates at Disney Land, and the teacher assistant tries to get everyone evenly spaced before the turnstile and going through at a constant rate. He can't hold people up so that they're standing in the parking lot, nor can he get people to run to the parking lot, but if the average flow is steady, he can provide an even stream of screaming children. Every off-the-shelf DAC has a PLL, though some are better than others, and it's quite possible that Theta's is better than most.  A better PLL requires a larger FIFO buffer, so to accommodate larger swings in the tide, so to speak, without having to compromise the new clock. For instance, if a CD was fed at 44,003 samples per second, a PLL would simply shift the master clock to 44,003 samples per second, not underrun the buffer, and still be able to attenuate the higher frequency jitter. This extreme example would result in a slight pitch shift, but where it gets really difficult is when it's shifting fast enough to cause modulation problems in the DAC, but slow enough to cause the FIFO buffer problems, an area where better jitter reduction schemes really shine.
    + x# ~$ _6 v. ?( J+ J3 u% w
  11. 6 f' l( ]% H$ o% D: }; V
  12. This extreme example would result in a slight pitch shift, but where it gets really difficult is when it's shifting fast enough to cause modulation problems in the DAC, but slow enough to cause the FIFO buffer problems. Although the PLL circuit is the best way to attenuate jitter while managing the FIFO buffer with poor sources, the strength of the PLL's continuity is also its weakness in jitter reduction. In order to avoid buffer overflows or underflow with low frequency variations, the PLL will adjust the clock to match the data rate over a particular period, and if that jitter period is large enough (low in frequency) to make the PLL circuit adopt the change in data rate, the clock essentially tracks the jitter, passing the same timing errors on, even if slightly attenuated.
    ) {( K" M, ], {# R
  13. 0 F: L* v2 \$ n
  14. It is here that we see that all PLL circuits are not created equal. A larger FIFO buffer, and possibly better buffer management in terms of how the clock adjusts to the amount of data in the buffer, mean that different PLL circuits have differing amounts of jitter attenuation, particularly in terms of low frequency jitter.  v' g/ g8 a) l9 i& |; Y2 Y

  15. 0 N' s$ x* b" z  _3 }# u: n
  16. With better jitter reduction methods, the input buffer and the PLL can manage more low-frequency jitter while still attenuating the lower frequency jitter, whereas a poorer PLL circuit will simply begin to let the clock follow the lower frequency jitter, essentially passing it right onto the DAC. Since it is the lower frequency jitter that's the most audible, this is where the better jitter reduction schemes really shine. They still follow the rate of the incoming data, but their clocks remain more stable and jitter free in the presence of a less desirable source.
    ) D7 Y9 _2 V) O6 J- M( l  F
复制代码

本帖子中包含更多资源

您需要 登录 才可以下载或查看,没有帐号?注册

x
回复 支持 反对

使用道具 举报

19#
 楼主| 发表于 2007-2-6 17:06 | 只看该作者
原帖由 酷风 于 2007-2-6 13:17 发表
+ A4 t6 a8 z9 j! e& R* |. t8 X) k( g, h! U5 G3 G4 Y
使用优质的独立时钟能否基本消除jitter?
- ~3 y2 Q' P5 _7 b
独立时钟不同于spdif信号的时钟。jitter就产生了。就是这种jitter最难对付。
回复 支持 反对

使用道具 举报

20#
发表于 2007-2-6 17:55 | 只看该作者
原帖由 zifzhu 于 2007-2-6 17:06 发表, j6 N5 k, l4 v/ W! f
* U7 L" M% k1 F
独立时钟不同于spdif信号的时钟。jitter就产生了。就是这种jitter最难对付。
; A$ i1 h8 X% K  y1 E
看来还是需要足够好的音源才能尽量减少jitter……那就麻烦多了……
回复 支持 反对

使用道具 举报

您需要登录后才可以回帖 登录 | 注册

本版积分规则

广告投放或合作|网站地图|处罚通告|

GMT+8, 2025-8-12 11:18

Powered by Discuz! X3.4

© 2001-2017 POPPUR.

快速回复 返回顶部 返回列表