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LZ去踩AMD和MS吧,这种中看不中用的技术就是AMD发布、MS推广的。
PS:现在的EMT64和X64毫无区别。
附:X86-64的说明
- Full support for 64-bit integers: All general-purposeregisters (GPRs) are expanded from 32 bits to 64 bits, and allarithmetic and logical operations, memory-to-register andregister-to-memory operations, etc., are now directly supported for64-bit integers. Pushes and pops on the stack are always in eight-bytestrides, and pointers are eight bytes wide.
- Additional registers:In addition to increasing the size of the general-purpose registers,the number of named general-purpose registers is increased from eight(i.e. eax,ebx,ecx,edx,ebp,esp,esi,edi) in x86-32to 16. It is therefore possible to keep more local variables inregisters rather than on the stack, and to let registers holdfrequently accessed constants; arguments for small and fast subroutinesmay also be passed in registers to a greater extent. However, moreregisters also involves more saving and restoring of register contents,and AMD64 still has fewer registers than many common RISC processors (which typically have 32–64 registers) or VLIW-like machines such as the IA-64 (which has 128 registers).
- Additional XMM (SSE) registers: Similarly, the number of 128-bit XMM registers (used for Streaming SIMD instructions) is also increased from 8 to 16.
- Larger virtual address space: Current processor models implementing the AMD64 architecture can address up to 256 tebibytes of virtual address space (248 bytes). This limit can be raised in future implementations to 16 exbibytes (264 bytes). This is compared to just 4 gibibytesfor 32-bit x86. This means that very large files can be operated on bymapping the entire file into the process' address space (which isgenerally faster than working with file read/write calls), rather thanhaving to map regions of the file into and out of the address space.
- Larger physical address space: Current implementations of the AMD64 architecture can address up to 1 tebibyte of RAM (240 bytes); the architecture permits extending this to 4 pebibytes (252 bytes) in the future (limited by the page table entry format). In legacy mode, Physical Address Extension (PAE) is supported, as it is on most current 32-bit x86 processors, allowing access to a maximum of 64 gibibytes.
- Instruction pointer relative data access: Instructions can now reference data relative to the instruction pointer (RIP register). This makes position independent code, as is often used in shared libraries and code loaded at run time, more efficient.
- SSE instructions: The original AMD64 architecture adopted Intel's SSE and SSE2 as core instructions. SSE3 instructions were added in April 2005. SSE2 replaces the x87 instruction set's IEEE 80-bit precision,with the choice of either IEEE 32-bit or 64-bit floating-pointmathematics. This provides floating-point operations compatible withmany other modern CPUs. The SSE and SSE2 instructions have also beenextended to support the eight new XMM registers. SSE and SSE2 areavailable in 32-bit mode in modern x86 processors; however, if they'reused in 32-bit programs, those programs will only work on systems withprocessors that support them. This is not an issue in 64-bit programs,as all processors that support AMD64 support SSE and SSE2, so using SSEand SSE2 instructions instead of x87 instructions does not reduce theset of machines on which the programs will run. Since SSE and SSE2 aregenerally faster than, and duplicate most of the features of, thetraditional x87 instructions, MMX, and 3DNow!, the latter are redundant under AMD64.
- No-Execute bit:The “NX” bit (bit 63 of the page table entry) allows the operatingsystem to specify which pages of virtual address space can containexecutable code and which cannot. An attempt to execute code from apage tagged "no execute" will result in a memory access violation,similar to an attempt to write to a read-only page. This should make itmore difficult for malicious code to take control of the system via "buffer overrun" or "unchecked buffer" attacks. A similar feature has been available on x86 processors since the 80286as an attribute of segment descriptors; however, this works only on anentire segment at a time. Segmented addressing has long been consideredan obsolete mode of operation, and all current PC operating systems ineffect bypass it, setting all segments to a base address of 0 and asize of 4 GiB.AMD was the first x86-family vendor to support no-execute in linearaddressing mode. The feature is also available in legacy mode on AMD64processors, and recent Intel x86 processors, when PAE is used.
- Removal of older features: A number of "system programming"features of the x86 architecture are not used in modern operatingsystems and are not available on AMD64 in long (64-bit andcompatibility) mode. These include segmented addressing (although theFS and GS segments were retained in vestigial form for compatibilitywith Windows code)[3],the task state switch mechanism, and Virtual-8086 mode. These featuresdo of course remain fully implemented in "legacy mode," thus permittingthese processors to run 32-bit and 16-bit operating systems withoutmodification.
和EMT64对比一下,有什么区别?
[ 本帖最后由 acqwer 于 2007-11-21 09:18 编辑 ] |
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