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AMD发布K8L微架构部分细节 添加90nm K8 die shot比较图 四内核面积只比Core2 Duo大7%

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1#
发表于 2006-5-17 09:15 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
Advanced Micro Devices will come out with a new chip architecture next year, and it's not messing with the basic formula that has helped it take market share away from Intel.

The new chip architecture--currently dubbed the Next Generation Processor Technology--enhances the design underlying the current Opteron, Turion and Athlon 64 chips. Performance will increase and AMD will keep a lid on power consumption, but the company has veered away from making radical conceptual changes in the overall blueprint. Processors built under the new design will come out in 2007.


"Rather than focus on coming out with a new core every other year, we're focusing on the big picture" of overall system performance, said Chuck Moore, a senior fellow at AMD.

Intel, by contrast, is overhauling the basic architecture of its chips in the second half of 2006 and will follow with more incremental design changes in subsequent years. The company asserts that processors based on the architecture--Merom, Conroe and Woodcrest, will substantially outdo contemporary AMD chips by 20 percent and reduce power consumption.

While Moore didn't make a point-for-point comparison with Intel's future chips, he asserted that right now AMD is beating the company he called AMD's nearest competitor.

"When you compare the performance and power consumption, there is an enormous difference," he said.

Which company comes out with the superior chip architecture over the next 18 months will be one of the big issues in the PC market in 2007 and will ultimately depend on a host of factors.

Chips built under the new AMD architecture will feature a faster version of HyperTransport, an input-output technology featured on AMD chips. HyperTransport 3.0, recently approved by the standards body that governs the development of the technology, will accomplish 5.2 gigatransfers (5.2 billion transfers of data) per second, Moore said. Although it doesn't get as much attention as 64-bit processing, HyperTransport is behind much of the performance gains of AMD chips in recent years.

The new chips will also sport four processing cores. AMD's best chips currently come with two processing cores.

One of the biggest changes will come in the caches, reservoirs of memory built into the processor for rapid data access. In current AMD chips, each core has two caches and those caches are completely dedicated to their respective cores. In future chips, each core will also have two dedicated caches, but the cores will also share a third cache. With the third cache, the processor will less often have to fetch data from main memory--a time-consuming process.

Intel chips typically have larger caches. Intel, however, does not integrate a memory controller onto its chips like AMD does. This also cuts down memory latency. Whether it's better to have a larger cache and a separate memory controller or a smaller cache with an integrated memory controller is the source of an ongoing debate between the two companies.

The upcoming AMD chips will also curb power consumption by allowing the memory controller or the processor core to independently power down during idle periods, Moore said. The memory controller and processing cores currently slow down during slow periods, but only when both are relatively idle.

The integrated memory controller on the new chips will also connect to DDR2 memory and accommodate DDR3, a memory specification under construction, at the appropriate time, Moore added. Intel will match its future server chips with another memory standard, called FB-DIMM. Again, which of these is better is under debate between the two companies. AMD says that FB-DIMM produces more heat.

An Intel representative said the amount of extra energy is minimal, adding that AMD won't support FB-DIMM faster than standard DDR memory because of the integrated memory controller.

Moore outlined AMD's plans at the Spring Processor Forum in San Jose, Calif.

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2#
 楼主| 发表于 2006-5-17 09:17 | 只看该作者
IN HIS KEYNOTE, AMD's Chuck Moore basically laid out the K8L in slightly more detail than we did. Either way, here are the highlights.

First, it has a shared expandable L3 cache, necessary because it is a native quad-core design. The one massive enhancement to the mix is that AMD finally has the ability to independently change core voltages for power savings. It now can also change the north bridge voltage independently of the cores. This is a huge win, we are told voltage differentials and problems with them were one of the main scaling headaches of the K8 core to this point.


Next is memory. The new core will support 48-bit addressing and 1GB pages. Cray and SGI will be very happy with this, until they hit that memory wall again. There is also official co-processor support, strongly hinted to be on a HTX card. The key here will be the platform is aware of them vs having to hack them in.

The other whopper Chuck dropped was that DDR2 is coming and DDR3 is in the wings when the spec 'settles down'. Old news, FB-DIMMs are the future, right? AMD has said they are supporting them, but the big news is that they are not forcing support. Unlike Intel's approach, Blackford supports only FBD, AMD will let you choose. This seems to strongly suggest that the controller on the later gens will be quite flexible indeed.

Next up is RAS, another area where AMD is sorely lacking. It is addressing the major sore points with support for memory mirroring, data poisoning support, and HT retry. It looks like it is following the IBM roadmap more than the Intel one here.

IPC is also going up in a big way. It is doing the obvious doubling of SSE/FP resources, old news now, but it goes a lot deeper than that. There are a bunch of added instructions, starting with the bit manipulation instructions LZCNT and POPCNT. It also added SSE extensions EXTRQ/INSERTQ and MOVNTSD/MOVNTSS. No word on SSE4 though.

The last bit is much more aggressive prefetch to 'feed the beast'. It has gone from 16B to 32B, an obvious step with the added SSE number crunching power. On top of this, it has out of order loads, and other tweaks to use the available bandwidth in a much more efficient manner.

For those who thought K8L was more or less a tweaked K8, you are wrong. It looks like no part of the core has been left unmolested by the elves working the CAD stations. It looks like AMD will have a credible response to the Intel MCW architecture after all. 2007 will be a fight after all. µ

我做了K8L和目前90nm dual core K8的die shot比较:

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3#
发表于 2006-5-17 10:07 | 只看该作者
4核心, 估计2008能发布...普及要等09年了
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4#
发表于 2006-5-17 10:40 | 只看该作者
K8L明年上半年上市。
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5#
发表于 2006-5-17 10:46 | 只看该作者
超过2倍的浮点性能很nb。同时兼容多种内存也很nb。
虚拟IO,不知道意味着什么,好像这个影响更大。
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6#
发表于 2006-5-17 10:52 | 只看该作者
原帖由 电脑是工具 于 2006-5-17 10:40 发表
K8L明年上半年上市。

虽说"2007 will be a fight after all"

可Am2出了样品, 唱了快一年了还没有动静, 你信K8L 2007上半年上市?
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7#
发表于 2006-5-17 11:08 | 只看该作者
原帖由 黑真PIG 于 2006-5-17 10:52 发表

虽说"2007 will be a fight after all"

可Am2出了样品, 唱了快一年了还没有动静, 你信K8L 2007上半年上市?


fans所以是fans,就是因为脑子坏掉了,自己都不知道自己在说什么。

AM2没动静?昨天刚发布了低功耗的AM2,一周后发布其他的AM2,这个月开始陆续供货。
AM2相比规划,延迟了大概2个月。65NM CD也延迟了一个半月,国内到现在都不知道去哪里找65nm的cpu。
K8L 08年才上市?  07年AMD卖K10吗。猪也不会说这样的话,但脑子坏掉的fans就会。
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8#
发表于 2006-5-17 11:18 | 只看该作者
原帖由 电脑是工具 于 2006-5-17 11:08 发表


fans所以是fans,就是因为脑子坏掉了,自己都不知道自己在说什么。

AM2没动静?昨天刚发布了低功耗的AM2,一周后发布其他的AM2,这个月开始陆续供货。
AM2相比规划,延迟了大概2个月。65NM CD也延迟了一个 ...

AMD从发布样品, 发布接口等等, 用了多久?  3个月前就有ES版了, 如今才发布. hoho

这种发布也是学ATI, 口头发布. 等一段时间才能铺货.

K8L目前只有文字资料, 连个图片都没有, 你说什么时候? :shifty:

而且K8L更要用AM3接口:sweatingbullets::sweatingbullets:

462 > 754 > 940 > 939 > AM2 > AM3 :sweatingbullets::sweatingbullets::sweatingbullets:

[ 本帖最后由 黑真PIG 于 2006-5-17 11:21 编辑 ]
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头像被屏蔽
9#
发表于 2006-5-17 11:22 | 只看该作者
全文看完~结论——新一 代硅渣:shifty:
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10#
发表于 2006-5-17 11:23 | 只看该作者
这种CPU,4核的估计真的没2008都出不来,纸上谈兵,谁都会啊,K8老了。。。。。。。。。。AMD的65纳秒看都没看到,别跟我说AMD用90NS做个4核心U。。。。。。。
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11#
发表于 2006-5-17 11:26 | 只看该作者
原帖由 ppzhong 于 2006-5-17 11:23 发表
这种CPU,4核的估计真的没2008都出不来,纸上谈兵,谁都会啊,K8老了。。。。。。。。。。AMD的65纳秒看都没看到,别跟我说AMD用90NS做个4核心U。。。。。。。

这是4月才定的开发计划而已 :a)

某些人就说2007 上半年4核心...  :sweatingbullets:

摆明学ATI, 先让fans YY去, 到时候慢慢延期啊延期...
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12#
 楼主| 发表于 2006-5-17 11:31 | 只看该作者
怎么说K8L没有图片呢?我在贴中已经给出了K8L管芯的图片。

此外,你们看到的消息发布并不等于说消息发布的时候才确定cpu设计,大部分情况下都是在此前一年就已经确定了,只不过是基于各种原因一直处于保密状态。

K8L在07年年中或者下半年推出的机会相当大。
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13#
发表于 2006-5-17 11:32 | 只看该作者
原帖由 Edison 于 2006-5-17 11:31 发表
怎么说K8L没有图片呢?我在贴中已经给出了K8L管芯的图片。

此外,你们看到的消息发布并不等于说消息发布的时候才确定cpu设计,大部分情况下都是在此前一年就已经确定了,只不过是基于各种原因一直处于保密状态 ...

虽然这样说, 但4核, 还是2008年比较相信 :lol:
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14#
 楼主| 发表于 2006-5-17 11:34 | 只看该作者
原帖由 黑真PIG 于 2006-5-17 11:32 发表

虽然这样说, 但4核, 还是2008年比较相信 :lol:


四内核的K8L die size只有150平方毫米,die size只是比双内核的Conroe大10平方毫米,明年推出的机会远远大于2008年。
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15#
发表于 2006-5-17 11:40 | 只看该作者
原帖由 Edison 于 2006-5-17 11:34 发表


四内核的K8L die size只有150平方毫米,die size只是比双内核的Conroe大10平方毫米,明年推出的机会远远大于2008年。

对我来说4核心还是梦想中的东西 :a)
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16#
 楼主| 发表于 2006-5-17 11:43 | 只看该作者
原帖由 黑真PIG 于 2006-5-17 11:40 发表

对我来说4核心还是梦想中的东西 :a)


it is not a dream。

K8L牺牲cache容量换取更多的core以及内存传输通道,设计出发点和Intel那种凭庞大产能是很不一样的。
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babystudio 该用户已被删除
17#
发表于 2006-5-17 11:44 | 只看该作者
提示: 作者被禁止或删除 内容自动屏蔽
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18#
发表于 2006-5-17 11:49 | 只看该作者
原帖由 babystudio 于 2006-5-17 11:44 发表
到那个时候Intel和AMD目前的处境相信会对调的

这个是服务器用的...

不是民用的:sweatingbullets:

最起码2007/2008 是这样

目前来看2006/2007 是靠AM2和扣肉鏖战...

[ 本帖最后由 黑真PIG 于 2006-5-17 11:51 编辑 ]
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19#
 楼主| 发表于 2006-5-17 11:52 | 只看该作者
原帖由 黑真PIG 于 2006-5-17 11:49 发表

这个是服务器用的...

不是民用的:sweatingbullets:


他们都是民用的,不是军用的。

150mm^2的die size非常不错,90nm Rev.F的die size是220mm^2,K8L的die size只有 90nm Rev.F dual core K8的68%左右。

换句话说,K8L制造成本是目前90nm双内核K8的68%。
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20#
发表于 2006-5-17 11:57 | 只看该作者
原帖由 Edison 于 2006-5-17 11:52 发表


他们都是民用的,不是军用的。

150mm^2的die size非常不错,90nm Rev.F的die size是220mm^2,K8L的die size只有 90nm Rev.F dual core K8的68%左右。

换句话说,K8L制造成本是目前90nm双内核K8的68%。

高频产品良品率高一些就好了

民用的意思是... 家用计算机/个人电脑 :a)
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