32nm HP的工艺性能比较

PRAM

厂的数量跟工艺先进与否没有必然联系。

intel晶圆厂总数可能不是最多的，不过300mm晶圆厂绝对是最多的 ...
xf-108 发表于 2010-9-18 20:23

intel现在还保留了2座200mm晶圆厂,分别是FAB17和IFO

PRAM

厂的数量跟工艺先进与否没有必然联系。

intel晶圆厂总数可能不是最多的，不过300mm晶圆厂绝对是最多的 ...
xf-108 发表于 2010-9-18 20:23

    这个你要看什么样的FAB,整个半导体业界，300MM FAB最多的是SAMSUNG,

Cc.

英特尔的工艺确实独步天下，无疑问的，这方面即使是IBM都无法比肩

xf-108

http://tieba.baidu.com/f?ct=3356 ... word=amd#7953650825

Afan定律：AMD可以随意屏蔽核心廉价卖，说明了AMD 45nm生产成本非常低。
          clarkdale/Gulftown那么小核心居然卖那么高天价，说明了intel 32nm生产成本非常高，良率非常低。

Afan原理：1、AMD史上价格定位最杯具，性能最窝囊的65nm系列是AMD史上猫利率最高的CPU。
           2、AMD 45nm电气性能比intel 32nm还强。

frankincense

Afan定律：AMD可以随意屏蔽核心廉价卖，说明了AMD 45nm生产成本非常低。
          clarkdale/Gulftow ...
xf-108 发表于 2010-9-20 01:10

AFAN公论:咱AMD上面有人(IBM)只要它动动指头,Intel就要玩完

PRAM

Afan定律：AMD可以随意屏蔽核心廉价卖，说明了AMD 45nm生产成本非常低。
          clarkdale/Gulftow ...
xf-108 发表于 2010-9-20 01:10

    所谓高性能的45NM,EOT相当于INTEL的90NM,电气性能是在at 1.0V and 200nA/um Ioff.得出的，而且PMOS性能不行。gate-first就是这儿搞不下去。所以这款45NM仅仅是研究用的

PRAM

For AMD, the goal was not only to shrink the physical dimensions but also to increase performance. Scaling transistors means better performance, but most of the dimensional scaling at 45 nm is related to gate and metal pitches rather than to length of the transistor gate or channel. The minimum gate length on Shanghai is 38 nm—a reduction of only seven percent from the 65-nm node. But the transistor performance is 19 percent better for the NFET and 23 percent better for the PFET compared with 65-nm generation transistors.


How'd they do that? The answer, in a word, is optimization. Although there are no new materials or techniques like adding an additional stressor for strained silicon engineering, AMD improved transistor performance by squeezing every last drop out of the performance-enhancing structures already in use at 65 nm. As usual, the starting point was a silicon-on-insulator (SOI) wafer as opposed to the bulk wafer technology used elsewhere. The rest of the transistor performance story relates to strain engineering.



On the NFET side, stress memorization stretches the n-channel, which is enhanced later in the process flow by the addition of a nitride tensile stress liner. The liner itself is scaled down at 45 nm to ensure the required strain is adequately supplied to the transistor channel to enhance electron mobility and subsequently increase the drive current. The gate-stack design is modified as well, with a new sidewall spacer design for 45nm.



The PFET performance improvement is more dramatic with drive current now up to 660 µA/µm compared with 510 µA/µm on 65-nm transistors. Again, this increased output current is the result of optimized compressive strain for the p-channel device. The new design of the PFET moves the embedded silicon-germanium source/drain regions closer to the channel to maximize the transfer of stress, thereby increasing hole mobility. Although shorter gate lengths are not driving the improvements, it is a reduction in dimensions that allows increased channel stress to provide the performance scaling. AMD 45-nm PFET design reduces the space from embedded

PRAM

We all want our Google results to come fast, so server-chip speed is important. Intel has a long history of pushing processor-speed performance ratings, and did so by designing transistors with high on currents to drive fan out gates quickly. In fact, Intel's 45-nm high-K metal gate transistors have the best peak drive currents on the market with 1.36µA/µm for NFETs and just over a milliamp for PFETs. Compared with Intel's speed-burners, a typical 45-nm transistor on AMD's Shanghai is a lot less powerful. I know very little about CPU benchmarks let alone server tests, but I know the speed performance for a Shanghai-based server would be limited at some point by the lower drive current available from the AMD 45-nm transistors.
The transistor drive current for AMD's 45-nm devices is much lower than that of the Intel HKMG transistors.

spinup

某些专业网站认为45nm的shanghai有23-24个FO4延迟。而intel的penryn则是18-20个FO4延迟。penryn最高大约3.3g。
根据这些数字如果amd的工艺只和intel相当，那shanghai连3g都应该爬不上........

acqwer

X5270 3.5G

只能到3G和只出到3G是2回事，装着看不到想不到是没用的。

xeon-pan

在这个交易和菜鸟的地方谈这个貌似假装...
直流电 发表于 2010-9-20 21:15

    这里曾经不是只有菜鸟的地方。你都05年注册的了，应该知道GZ。。。

skywalker_hao

一份半年前就应该人手一份的会议摘要被拿来当宝每天挤一点出来显眼

skywalker_hao

X5270 3.5G

只能到3G和只出到3G是2回事，装着看不到想不到是没用的。
acqwer 发表于 2010-9-20 22:29

xeon总会有一款要高一点的嘛

不过5270和5272还不够震撼
3.4G的5492才震撼嘛
对比9775

PRAM

某些专业网站认为45nm的shanghai有23-24个FO4延迟。而intel的penryn则是18-20个FO4延迟。penryn最 ...
spinup 发表于 2010-9-20 22:13

    你就YY下去吧

PRAM

一份半年前就应该人手一份的会议摘要被拿来当宝每天挤一点出来显眼
skywalker_hao 发表于 2010-9-21 10:03

    不知道是谁在显眼，

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PRAM

一份半年前就应该人手一份的会议摘要被拿来当宝每天挤一点出来显眼
skywalker_hao 发表于 2010-9-21 10:03

    不知道是谁在显眼，丢人也要有个度，后面这个是反向分析得出的结论

PRAM

ee.letters 入伍新兵 名誉值1  工作领域 工作年资 个人空间 发短消息 加为好友 当前在线  1# 大 中 小 发表于 2009-3-19 16:43  只看该作者 求助: High-k gate-first 与High-k first, metal gate last比较? 目前只了解: IBM alliance:  High-k gate-first, 工艺简单,与原有工艺类同, Intel: High-k first, metal gate last, 性能好 x 不知道 对不对., 到底区别有哪些? 好处在哪? IBM联盟有用metal gate呀. 为什么提的很少呢? 谢谢! 搜索更多相关主题的帖子: gate metal first last 求助 UID252313 帖子121 精华0 积分8 金币17  名誉值1  在线时间116 小时 注册时间2006-7-27 最后登录2010-8-19 查看详细资料 引用 报告 评分 回复 TOP 人生有多少价值，端视帮助多少人创造价值！ tellmewhy 论坛版主 名誉值50  工作领域PIE 工作年资4年 个人空间 发短消息 加为好友 当前离线  2# 大 中 小 发表于 2009-3-20 09:50  只看该作者 IBM联盟metal gate只在32nm以下用，并且至今也不成熟，所以提得很少，前2个问题暂时不能回答你，因为涉及到某些机密以前有一个半导体工程师，非常认真负责，任何data都仔细check，老板压的AR都最快最完美的解决，无论多难的case，都能顺利的close，每天不做完事情坚决不肯走，终于有一天他。。。。。。。。。。。。。。。。。。。。。。。。。。挂了

PRAM

xeon总会有一款要高一点的嘛

不过5270和5272还不够震撼
3.4G的5492才震撼嘛
对比9775
skywalker_hao 发表于 2010-9-21 10:12

    电气性能和时钟频有必然关系？当年90NM P4 跑3.8G，现在45NM I7 3,4G，原来90NM比45NM性能还高啊

PRAM

某些专业网站认为45nm的shanghai有23-24个FO4延迟。而intel的penryn则是18-20个FO4延迟。penryn最 ...
spinup 发表于 2010-9-20 22:13

    时钟频率由PLL决定