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CPUPA6T
Superscalar, out-of-order 32-bit/64-bit Power Architecture processor core
Adheres to the Power ISA v.2.04
Little endian or big endian operation
64/64 kB instruction and data L1 caches. 32 GB/s bandwidth.
Six execution units including a double precision FPU and Altivec unit
Hypervisor and virtualization support
Maximum 7 W at 2 GHz
11 million transistors, 10 mm² large @ 65 nm.[edit] Memory systemCONEXIUM
scalable cross-bar interconnect
1–8 SMP cores
1–2 L2 caches, 512 KiB – 8 MiB large. 16 GB/s bandwidth.
1–4 1067 MHz DDR2 memory controllers. 16 GB/s bandwidth.
64 GB/s peak bandwidth
MOESI coherency
[edit] I/OENVOI
Centralized DMA engine, 32 GB/s bandwidth
16–64 SerDes lanes
XAUI
PCI Express
SGMII
Offload engine for cryptography, RAID, TCP
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